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    Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region
    11.
    发明申请
    Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region 有权
    用于形成具有低电阻通道区域的平面栅场效应晶体管的结构和方法

    公开(公告)号：US20110215377A1

    公开(公告)日：2011-09-08

    申请号：US13103728

    申请日：2011-05-09

    Applicant: James Pan ,  Qi Wang

    Inventor： James Pan ,  Qi Wang

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

    Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

    Abstract translation: 垂直导电的平面栅极场效应晶体管包括第一导电类型的硅区域，在硅区域上延伸的硅 - 锗层，横向延伸但与硅 - 锗层绝缘的栅电极，主体区域 在硅 - 锗层和硅区域中延伸的第二导电类型以及在硅 - 锗层中延伸的第一导电类型的源极区域。 栅极电极横向重叠源极和主体区域，使得在源极区域和主体区域的外边界之间直接在栅电极下方延伸的硅锗层的一部分形成沟道区域。

    Structure and method for forming field effect transistor with low resistance channel region
    13.
    发明授权
    Structure and method for forming field effect transistor with low resistance channel region 有权
    用于形成具有低电阻通道区域的场效应晶体管的结构和方法

    公开(公告)号：US07825465B2

    公开(公告)日：2010-11-02

    申请号：US12330273

    申请日：2008-12-08

    Applicant: James Pan ,  Qi Wang

    Inventor： James Pan ,  Qi Wang

    IPC: H01L29/78

    CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

    Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

    Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个主体区域与硅区域形成第一PN结，并且每个主体区域包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。 第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。 通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。 硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。

    Shielded gate trench FET with multiple channels
    14.
    发明授权
    Shielded gate trench FET with multiple channels 有权
    多通道屏蔽栅沟槽FET

    公开(公告)号：US07772668B2

    公开(公告)日：2010-08-10

    申请号：US11964283

    申请日：2007-12-26

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/93

    CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

    Abstract: A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

    Abstract translation: 场效应晶体管（FET）包括延伸到半导体区域中的一对沟槽。 每个沟槽包括在沟槽的下部中的第一屏蔽电极和在沟槽的上部中的与屏蔽电极绝缘的栅电极。 第一导电类型的第一和第二阱区域在该对沟槽之间的半导体区域中横向延伸并邻接该对沟槽的侧壁。 第一和第二阱区域通过第二导电类型的第一漂移区域彼此垂直间隔开。 栅电极和第一屏蔽电极相对于第一阱区和第二阱区定位，使得当FET被置于导通状态时，在第一和第二阱区中的每一个中形成沟道。

    Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance
    15.
    发明申请
    Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance 审中-公开
    用于形成具有低栅极电阻的沟槽栅极晶体管的结构和方法

    公开(公告)号：US20100013009A1

    公开(公告)日：2010-01-21

    申请号：US12333707

    申请日：2008-12-12

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66734 ,  H01L29/7397

    Abstract: A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench.

    Abstract translation: 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的主体区域，使得主体区域与半导体区域形成p-n结。 沟槽延伸穿过身体区域并终止在半导体区域内。 第二导电类型的源极区域在与沟槽相邻的主体区域上延伸，使得源极区域与主体区域形成p-n结。 栅极电介质层对每个沟槽的侧壁进行排列。 金属衬垫在每个沟槽中排列栅极电介质层。 包括金属材料的栅电极设置在每个沟槽中。

    Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices
    16.
    发明申请
    Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices 有权
    用于形成用于沟槽栅极器件的厚底电介质（TBD）的结构和方法

    公开(公告)号：US20090315083A1

    公开(公告)日：2009-12-24

    申请号：US12143510

    申请日：2008-06-20

    Applicant: James Pan ,  Christopher Lawrence Rexer

    Inventor： James Pan ,  Christopher Lawrence Rexer

    IPC: H01L29/00 ,  H01L21/76

    CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

    Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

    Abstract translation: 包括沟槽栅极FET的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。

    Methods for fabricating an integrated circuit
    17.
    发明授权
    Methods for fabricating an integrated circuit 有权
    制造集成电路的方法

    公开(公告)号：US07622348B2

    公开(公告)日：2009-11-24

    申请号：US11616858

    申请日：2006-12-28

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L21/8242

    CPC classification number: H01L21/76897 ,  H01L21/28568 ,  H01L21/288 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

    Abstract translation: 提供了用于在制造包括逻辑和存储器的IC中减小与位线的触点的纵横比的方法。 该方法包括以下步骤：形成将由金属的第一级接触的第一组器件区域和与第二级金属接触的第二组存储器位线，该第一级与第二级与第二级分开 至少一层介电材料。 导电材料通过化学镀在器件区域和位线上进行电镀，并且第一和第二导电插塞形成在导电材料上。 第一导电插头与第一级金属接触，第二导电插头与第二级金属接触。 镀覆的导电材料的厚度提供了一种自对准的方法，用于减小导电插头的纵横比。

    Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region
    18.
    发明申请
    Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region 有权
    用于形成具有低电阻通道区域的场效应晶体管的结构和方法

    公开(公告)号：US20090194811A1

    公开(公告)日：2009-08-06

    申请号：US12330273

    申请日：2008-12-08

    Applicant: James Pan ,  Qi Wang

    Inventor： James Pan ,  Qi Wang

    IPC: H01L29/78

    CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

    Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

    Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个体区与硅区形成第一PN结，并且每个体区包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。 第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。 通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。 硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。

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