公开(公告)号：US20090315083A1

公开(公告)日：2009-12-24

申请号：US12143510

申请日：2008-06-20

Applicant: James Pan ,  Christopher Lawrence Rexer

Inventor： James Pan ,  Christopher Lawrence Rexer

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract translation: 包括沟槽栅极FET的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。

公开(公告)号：US08669623B2

公开(公告)日：2014-03-11

申请号：US12870600

申请日：2010-08-27

Applicant: James Pan ,  Christopher Lawrence Rexer

Inventor： James Pan ,  Christopher Lawrence Rexer

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Abstract translation: 包括屏蔽栅极的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。 屏蔽电极形成在每个沟槽的底部。 在每个沟槽中的屏蔽电极之上形成栅电极。

公开(公告)号：US20100320534A1

公开(公告)日：2010-12-23

申请号：US12870600

申请日：2010-08-27

Applicant: James Pan ,  Christopher Lawrence Rexer

Inventor： James Pan ,  Christopher Lawrence Rexer

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Abstract translation: 包括屏蔽栅极的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。 屏蔽电极形成在每个沟槽的底部。 在每个沟槽中的屏蔽电极之上形成栅电极。

公开(公告)号：US20150230670A1

公开(公告)日：2015-08-20

申请号：US14181688

申请日：2014-02-16

Applicant: James Pan

Inventor： James Pan

IPC: A47K10/04 ,  A47B45/00

CPC classification number: A47K10/04 ,  A47B43/006 ,  A47K10/10

Abstract: The present invention is about an elastic extensible rack for bathroom towels, curtains, or paper tissue rolls. Elastic devices are attached to the two ends of the rack. The distance between the rack and the wall is flexible due to such elastic devices. The rack itself can be divided to multiple sections like a telescope. There is an elastic device attached to each section so the entire length of the rack is adjustable.

Abstract translation: 本发明涉及一种用于浴室毛巾，窗帘或纸巾卷的弹性可伸缩架。 弹性装置连接到机架的两端。 由于这种弹性装置，机架和墙壁之间的距离是柔性的。 机架本身可以分为多个部分，如望远镜。 每个部分都有一个弹性装置，所以机架的整个长度是可调的。

公开(公告)号：US20120291932A1

公开(公告)日：2012-11-22

申请号：US13113053

申请日：2011-05-22

Applicant: James Pan

Inventor： James Pan

IPC: B60B33/00

CPC classification number: B60B33/00 ,  B60B9/08 ,  B60B9/12 ,  B60B9/26 ,  B60B2200/45 ,  B60B2900/313 ,  B60B2900/911 ,  B60Y2200/83

Abstract: The present invention is about an oval or asymmetric wheel design for luggage bags. The wheel is in an ellipsoidal configuration. Suspension, cushion, or elastic devices are installed in the oval wheels. These devices, when compressed by the weight of the luggage bag, store energy. When the luggage bag is shifted in the subsequent phase of the motion by the traveler, the energy in the devices is released from the cushion, and pushes the luggage toward the intended direction.

Abstract translation: 本发明涉及用于行李箱的椭圆形或不对称轮设计。 车轮处于椭圆形配置。 悬挂，缓冲或弹性装置安装在椭圆轮中。 这些装置在被行李箱的重量压缩时储存能量。 当行李箱在随后的移动阶段中移动时，装置中的能量从缓冲垫中释放，并将行李推向预期的方向。

公开(公告)号：US20120280293A1

公开(公告)日：2012-11-08

申请号：US13550216

申请日：2012-07-16

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In accordance with an embodiment, a method of forming a semiconductor structure can include forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region, and forming a first diffusion barrier region disposed between the source region and the well region. The method can include forming a heavy body region of the second conductivity type in the well region and forming a second diffusion bather region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. The method can also include forming a gate electrode, and forming a dielectric insulating the gate electrode from the semiconductor region.

Abstract translation: 根据实施例，形成半导体结构的方法可以包括在半导体区域内在第二导电类型的阱区域中形成第一导电类型的源极区域，以及形成设置在源区域之间的第一扩散阻挡区域 和井区。 该方法可以包括在井区域中形成第二导电类型的重体区域，并形成具有不同于底部部分的厚度的厚度的重体区域侧部分的第二扩散浴室区域 的重体区域。 该方法还可以包括形成栅电极，以及形成从半导体区域绝缘​​栅电极的介质。

公开(公告)号：US08278702B2

公开(公告)日：2012-10-02

申请号：US12211654

申请日：2008-09-16

Applicant: James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

Inventor： James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397

Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

Abstract translation: 半导体结构包括延伸到半导体区域中的沟槽。 半导体区域的部分在形成台面区域的相邻沟槽之间延伸。 栅电极在每个沟槽中。 第一导电类型的阱区在相邻沟槽之间的半导体区域中延伸。 第二导电类型的源极区位于阱区中。 第一导电类型的重体区域在井区域中。 源极区域和重体区域是相邻的沟槽侧壁，并且重体区域沿着沟槽侧壁延伸到源区域上方到台面区域的顶表面。

公开(公告)号：US08278686B2

公开(公告)日：2012-10-02

申请号：US13103728

申请日：2011-05-09

Applicant: James Pan ,  Qi Wang

Inventor： James Pan ,  Qi Wang

IPC: H01L29/10 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Abstract translation: 垂直导电的平面栅极场效应晶体管包括第一导电类型的硅区域，在硅区域上延伸的硅 - 锗层，横向延伸但与硅 - 锗层绝缘的栅电极，主体区域 在硅 - 锗层和硅区域中延伸的第二导电类型以及在硅 - 锗层中延伸的第一导电类型的源极区域。 栅极电极横向重叠源极和主体区域，使得在源极区域和主体区域的外边界之间直接在栅电极下方延伸的硅锗层的一部分形成沟道区域。

公开(公告)号：US08253194B2

公开(公告)日：2012-08-28

申请号：US12212489

申请日：2008-09-17

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Abstract translation: 半导体结构包括半导体区域中的第一导电类型的漂移区域。 第二导电类型的阱区域在漂移区域之上。 第一导电类型的源极区位于阱区的上部。 第二导电类型的重体区域在阱区域中延伸。 重体区域的掺杂浓度高于阱区域。 至少部分地围绕重体区域的第一扩散阻挡区域。 栅电极通过栅极电介质与半导体区域绝缘​​。

公开(公告)号：US20120064073A1

公开(公告)日：2012-03-15

申请号：US13270006

申请日：2011-10-10

Applicant: Jian Chen ,  Ellen Fllvaroff ,  Sherman Fong ,  Dorothy French ,  Audrey Goddard ,  Paul J. Godowski ,  J. Christopher Grimaldi ,  Austin L. Gurney ,  Kenneth J. Hillan ,  Sarah G. Hymowitz ,  Hanzhong Li ,  James Pan ,  Melissa A. Starovasnik ,  Daniel Tumas ,  Menno Van Lookeren ,  Richard Vandlen ,  Colin K. Watanabe ,  P. Mickey Williams ,  William I. Wood ,  Daniel G. Yansura

Inventor： Jian Chen ,  Ellen Fllvaroff ,  Sherman Fong ,  Dorothy French ,  Audrey Goddard ,  Paul J. Godowski ,  J. Christopher Grimaldi ,  Austin L. Gurney ,  Kenneth J. Hillan ,  Sarah G. Hymowitz ,  Hanzhong Li ,  James Pan ,  Melissa A. Starovasnik ,  Daniel Tumas ,  Menno Van Lookeren ,  Richard Vandlen ,  Colin K. Watanabe ,  P. Mickey Williams ,  William I. Wood ,  Daniel G. Yansura

IPC: A61K39/395 ,  A61P19/02 ,  A61P11/06 ,  A61P17/00 ,  A61P17/06 ,  A61P37/08 ,  A61P29/00 ,  A61P1/00

CPC classification number: C07K16/244 ,  A61K38/00 ,  C07H21/04 ,  C07K14/54 ,  C07K14/7155 ,  C07K2317/21 ,  C07K2317/24 ,  C07K2317/35 ,  C07K2317/54 ,  C07K2317/55 ,  C07K2317/62 ,  G01N33/505 ,  G01N33/564 ,  G01N33/574 ,  G01N33/57407 ,  G01N33/57423 ,  G01N33/57438 ,  G01N33/57492 ,  G01N2333/54 ,  G01N2333/7155

Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.

Abstract translation: 本发明涉及与IL-17，IL-17受体和编码那些多肽的核酸分子具有序列同一性的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。 本文还提供了治疗退行性软骨疾病和其它炎性疾病的方法。