利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.025 秒)

    Three-dimensional semiconductor memory devices
    11.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10038009B2

    公开(公告)日：2018-07-31

    申请号：US15662714

    申请日：2017-07-28

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor.

    Semiconductor Devices and Methods for Forming the Same
    12.
    发明申请
    Semiconductor Devices and Methods for Forming the Same 审中-公开

    公开(公告)号：US20170323901A1

    公开(公告)日：2017-11-09

    申请号：US15661718

    申请日：2017-07-27

    申请人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    发明人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

    Semiconductor device
    13.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09548316B2

    公开(公告)日：2017-01-17

    申请号：US14959209

    申请日：2015-12-04

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Sunghoon Bae ,  Jaesun Yun ,  Kyu-Baik Chang

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Sunghoon Bae ,  Jaesun Yun ,  Kyu-Baik Chang

    IPC分类号： H01L27/12 ,  H01L27/115 ,  H01L27/06

    CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11575

    摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

    摘要翻译： 半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构 以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

    SEMICONDUCTOR DEVICES
    15.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20170330894A1

    公开(公告)日：2017-11-16

    申请号：US15662714

    申请日：2017-07-28

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

    Semiconductor device having interconnection line
    18.
    发明授权
    Semiconductor device having interconnection line 有权
    具有互连线的半导体器件

    公开(公告)号：US09263576B2

    公开(公告)日：2016-02-16

    申请号：US14576257

    申请日：2014-12-19

    申请人： Jang-Gn Yun ,  Hoo-Sung Cho ,  Jae-Sun Yun

    发明人： Jang-Gn Yun ,  Hoo-Sung Cho ,  Jae-Sun Yun

    IPC分类号： H01L21/8242 ,  H01L29/78 ,  H01L23/528 ,  H01L29/36 ,  H01L27/088

    CPC分类号： H01L29/7827 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

    摘要翻译： 提供一种半导体器件。 半导体器件包括沿第一方向延伸的绝缘层。 第一垂直通道柱与绝缘层分开设置。 第一互连线在垂直于第一方向的第二方向上延伸，并且电连接到第一垂直通道柱。 第一位线在第二方向上延伸，并跨过第一互连线和第一垂直通道支柱。 第一位触点与第一互连线重叠，并且将第一互连线电连接到第一位线。 在第二方向上的第一位触点的长度大于第一方向上的第一位触点的长度。

    SEMICONDUCTOR DEVICES
    20.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20180337193A1

    公开(公告)日：2018-11-22

    申请号：US16047712

    申请日：2018-07-27

    申请人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    发明人： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

    IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor