公开(公告)号：US20180337193A1

公开(公告)日：2018-11-22

申请号：US16047712

申请日：2018-07-27

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US20160163635A1

公开(公告)日：2016-06-09

申请号：US14957113

申请日：2015-12-02

Applicant: Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

Inventor： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L27/115

CPC classification number: H01L23/528 ,  H01L23/3192 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

Abstract translation: 半导体器件包括设置在半导体衬底上的单元半导体图案。 在半导体衬底上设置半导体虚设图案。 半导体虚拟图案与单元半导体图案共面。 第一电路设置在半导体衬底和单元半导体图案之间。 第一互连结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构的一部分与第一互连结构的一部分共面。 与半导体图案不重叠的第二虚拟结构设置在半导体衬底上。 第二虚拟结构的一部分与第一互连结构的一部分共面。 在电池半导体图案和半导体衬底之间以及第一电路和第一互连结构之上设置导电屏蔽图案。

公开(公告)号：US09741733B2

公开(公告)日：2017-08-22

申请号：US14962263

申请日：2015-12-08

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

公开(公告)号：US09728549B2

公开(公告)日：2017-08-08

申请号：US14974567

申请日：2015-12-18

Applicant: Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

Inventor： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US10038009B2

公开(公告)日：2018-07-31

申请号：US15662714

申请日：2017-07-28

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor.

公开(公告)号：US09548316B2

公开(公告)日：2017-01-17

申请号：US14959209

申请日：2015-12-04

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Sunghoon Bae ,  Jaesun Yun ,  Kyu-Baik Chang

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Sunghoon Bae ,  Jaesun Yun ,  Kyu-Baik Chang

IPC: H01L27/12 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

Abstract translation: 半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构 以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

公开(公告)号：US20170330894A1

公开(公告)日：2017-11-16

申请号：US15662714

申请日：2017-07-28

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US09887199B2

公开(公告)日：2018-02-06

申请号：US14670667

申请日：2015-03-27

Applicant: Joon-Sung Lim ,  Jang-Gn Yun ,  Hoosung Cho

Inventor： Joon-Sung Lim ,  Jang-Gn Yun ,  Hoosung Cho

IPC: H01L27/088 ,  H01L27/105 ,  H01L27/06 ,  H01L27/11524 ,  H01L27/11582 ,  G11C5/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: H01L27/105 ,  G11C5/025 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a peripheral circuit region and a first memory region that are side by side on a substrate. Moreover, the semiconductor device includes a second memory region that is on the peripheral circuit region and the first memory region. Related methods of programming semiconductor devices are also provided.

公开(公告)号：US10249636B2

公开(公告)日：2019-04-02

申请号：US15692606

申请日：2017-08-31

Applicant: Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

Inventor： Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11565

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US09786676B2

公开(公告)日：2017-10-10

申请号：US15217313

申请日：2016-07-22

Applicant: Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

Inventor： Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.