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45 条记录 (耗时 0.036 秒)

    Bitline hard mask spacer flow for memory cell scaling
    12.
    发明授权
    Bitline hard mask spacer flow for memory cell scaling 有权
    位线硬掩模间隔流程用于存储单元缩放

    公开(公告)号：US06927145B1

    公开(公告)日：2005-08-09

    申请号：US10770673

    申请日：2004-02-02

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Jaeyong Park ,  Tazrien Kamal ,  Emmanuil H. Lingunis

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Jaeyong Park ,  Tazrien Kamal ,  Emmanuil H. Lingunis

    IPC分类号： H01L21/027 ,  H01L21/761 ,  H01L21/8246 ,  H01L27/115

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.

    摘要翻译： 本发明是半导体器件和形成半导体器件的方法。 半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

    Memory manufacturing process with bitline isolation
    13.
    发明授权
    Memory manufacturing process with bitline isolation 有权
    内存制造过程采用位线隔离

    公开(公告)号：US08673716B2

    公开(公告)日：2014-03-18

    申请号：US10118732

    申请日：2002-04-08

    申请人： Mark T. Ramsbey ,  Tazrien Kamal ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Yu Sun

    发明人： Mark T. Ramsbey ,  Tazrien Kamal ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Yu Sun

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

    摘要翻译： 集成电路的制造方法具有具有芯区域和周边区域的半导体基板。 在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。 位线在芯区域中的半导体衬底中而不是在周边区域中形成。 在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。 形成了一条字和门。 源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

    Hard mask process for memory device without bitline shorts
    15.
    发明授权
    Hard mask process for memory device without bitline shorts 有权
    内存设备的硬掩模处理，无位线短路

    公开(公告)号：US06706595B2

    公开(公告)日：2004-03-16

    申请号：US10100485

    申请日：2002-03-14

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

    摘要翻译： 用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 生长自杀剂不会使第一和第二位线短路。

    Semiconductor memory with data retention liner
    17.
    发明授权
    Semiconductor memory with data retention liner 有权
    具有数据保留衬垫的半导体存储器

    公开(公告)号：US07297592B1

    公开(公告)日：2007-11-20

    申请号：US11195201

    申请日：2005-08-01

    申请人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

    发明人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L21/3185 ,  H01L27/11568

    摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

    摘要翻译： 一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。 层间绝缘层沉积在数据保持衬里上。

    Narrow bitline using Safier for mirrorbit
    18.
    发明授权
    Narrow bitline using Safier for mirrorbit 有权
    使用Safier进行镜像位的窄位线

    公开(公告)号：US06872609B1

    公开(公告)日：2005-03-29

    申请号：US10755430

    申请日：2004-01-12

    申请人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh

    发明人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh

    IPC分类号： H01L21/337 ,  H01L21/8246 ,  H01L27/115

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

    摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 在形成过程中采用Safier材料以减小存储器中的埋置位线的尺寸，其适用于存储用于计算机等的数据。 较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。 位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。 以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。 此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。