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    Bitline hard mask spacer flow for memory cell scaling
    1.
    发明授权
    Bitline hard mask spacer flow for memory cell scaling 有权
    位线硬掩模间隔流程用于存储单元缩放

    公开(公告)号：US06927145B1

    公开(公告)日：2005-08-09

    申请号：US10770673

    申请日：2004-02-02

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Jaeyong Park ,  Tazrien Kamal ,  Emmanuil H. Lingunis

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Jaeyong Park ,  Tazrien Kamal ,  Emmanuil H. Lingunis

    IPC分类号： H01L21/027 ,  H01L21/761 ,  H01L21/8246 ,  H01L27/115

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.

    摘要翻译： 本发明是半导体器件和形成半导体器件的方法。 半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance
    2.
    发明授权
    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
    制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法

    公开(公告)号：US06855608B1

    公开(公告)日：2005-02-15

    申请号：US10463643

    申请日：2003-06-17

    申请人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    发明人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/11573

    摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

    摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间​​露出衬底，并且在其上制造导体以增强每个位线的导电性。

    Alignment marks with salicided spacers between bitlines for alignment signal improvement
    6.
    发明授权
    Alignment marks with salicided spacers between bitlines for alignment signal improvement 有权
    对准标记与位线之间的水平间隔物，用于对准信号改善

    公开(公告)号：US07098546B1

    公开(公告)日：2006-08-29

    申请号：US10869286

    申请日：2004-06-16

    申请人： Emmanuil H. Lingunis ,  Jean Yee-Mei Yang ,  Hidehiko Shiraiwa

    发明人： Emmanuil H. Lingunis ,  Jean Yee-Mei Yang ,  Hidehiko Shiraiwa

    IPC分类号： H01L23/544 ,  H01L21/76

    CPC分类号： H01L27/115 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/11568 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.

    摘要翻译： 本发明涉及在半导体制造中利用硅化物建立对准标记。 在硅衬底的暴露部分上形成金属层，以及形成在衬底内的位线之间形成的氧化物区域。 处理金属层与硅衬底的暴露部分反应以形成咸水区域。 然而，金属层不与氧化物区域反应。 因此，在氧化物区域附近形成有咸水区域，以在其上照射光时提供增强的光学对比度。 以这种方式，对准标记可以更容易地“看到”。 因此，增强的光学对比度允许标记继续被看作是发生缩放。

    Recessed channel
    8.
    发明授权
    Recessed channel 有权
    嵌入渠道

    公开(公告)号：US06963108B1

    公开(公告)日：2005-11-08

    申请号：US10683631

    申请日：2003-10-10

    申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/04 ,  H01L29/78 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/045 ,  H01L29/66621 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/792

    摘要： A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.

    摘要翻译： 描述了具有减小的短通道效应的存储单元。 在半导体衬底中形成沟槽区。 源极区域和漏极区域形成在沟槽区域的相对侧上，其中源极区域的底部和漏极区域的底部在沟槽区域的地板的上方。 在源极区域和漏极区域之间的半导体衬底的沟槽区域中形成栅极电介质层。 在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。 控制栅极形成在凹陷沟道区域上方的半导体衬底上，其中控制栅极通过栅极介电层与凹陷沟道区分离。

    RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist
    9.
    发明授权
    RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist 失效
    RELACS收缩方法应用于使用化学放大DUV型光致抗蚀剂的LDD或埋入式位线植入物的单面抗蚀剂掩模

    公开(公告)号：US06642148B1

    公开(公告)日：2003-11-04

    申请号：US10126326

    申请日：2002-04-19

    申请人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

    发明人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

    IPC分类号： H01L21302

    CPC分类号： H01L29/6659 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11568

    摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

    摘要翻译： 本发明一般涉及一种在半导体衬底内形成渐变结的方法。 在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。 半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。 第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。 然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。