Metal capacitor design for improved reliability and good electrical connection
    11.
    发明授权
    Metal capacitor design for improved reliability and good electrical connection 有权
    金属电容设计,提高可靠性和良好的电气连接

    公开(公告)号:US08357584B2

    公开(公告)日:2013-01-22

    申请号:US12615796

    申请日:2009-11-10

    IPC分类号: H01L21/20

    摘要: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.

    摘要翻译: 形成对电容器的两个节点具有良好导电性的金属电容器,并提高可靠性。 一个实施例包括交替的第一和第二金属线的第一层,交替的第三和第四金属线的第二层,第一和第二层之间的介电层,以及介电层中的通孔,将第一和第二金属线与 第三和第四金属线,其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段,第一宽度大于第二宽度,每个第一段邻近相邻的第二段的第二段 金属线,并且仅金属线的第一段与通孔重叠。 该设计使得能够保持金属线之间的间距,通孔与金属之间的间隔增加,并且通过两个网络的连接来保持,从而提高电容器的导电性和可靠性并保持电容密度。

    System for characterization of low-k dielectric material damage
    13.
    发明授权
    System for characterization of low-k dielectric material damage 有权
    低k电介质损伤表征系统

    公开(公告)号:US07576357B1

    公开(公告)日:2009-08-18

    申请号:US11259572

    申请日:2005-10-26

    申请人: Jianhong Zhu David Wu

    发明人: Jianhong Zhu David Wu

    IPC分类号: H01L23/58

    摘要: A method of detecting damage to at least one dielectric layer in an IC die by determining a capacitance factor. The capacitance factor can be used to determine damage in a low-k dielectric material. A system for detecting damage can include a conductive line structure for measuring capacitance and software or a device for determining the capacitance to determine the damage.

    摘要翻译: 一种通过确定电容因子来检测IC芯片中的至少一个电介质层的损伤的方法。 电容因数可用于确定低k电介质材料的损伤。 用于检测损伤的系统可以包括用于测量电容和软件的导线结构或用于确定电容以确定损坏的装置。

    Method and system for treating a dielectric film
    14.
    发明授权
    Method and system for treating a dielectric film 失效
    电介质膜处理方法及系统

    公开(公告)号:US07345000B2

    公开(公告)日:2008-03-18

    申请号:US11060352

    申请日:2005-02-18

    IPC分类号: H01L21/31

    摘要: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue. Moreover, preparation for barrier layer and metallization of features in the film may include treating by performing sealing of sidewall surfaces of the feature to close exposed pores and provide a surface for barrier film deposition.

    摘要翻译: 用于处理电介质膜的方法和系统包括将电介质膜的至少一个表面暴露于烷基硅烷,烷氧基硅烷,烷基硅氧烷,烷氧基硅氧烷,芳基硅烷,酰基硅烷,环硅氧烷,聚倍半硅氧烷(PSS ),芳基硅氧烷,酰基硅氧烷或卤代硅氧烷,或其任何组合。 介电膜可以包括具有或不具有在干蚀刻处理之后形成的蚀刻特征的孔的低介电常数膜。 作为蚀刻处理或灰化的结果,形成在电介质膜中的特征中的暴露表面可能被损坏或激活,导致污染物的保留,水分的吸收,介电常数的增加等。损坏的表面,例如这些 通过执行愈合这些表面中的至少一个来处理,例如恢复介电常数(即,降低介电常数)并清洁这些表面以去除污染物,水分或残留物。 此外,膜的特征的阻挡层和金属化的制备可以包括通过执行特征的侧壁表面的密封来封闭暴露的孔并提供用于阻挡膜沉积的表面来进行处理。

    MOS structures with remote contacts and methods for fabricating the same
    16.
    发明授权
    MOS structures with remote contacts and methods for fabricating the same 有权
    具有远程触点的MOS结构及其制造方法

    公开(公告)号:US07989891B2

    公开(公告)日:2011-08-02

    申请号:US11755930

    申请日:2007-05-31

    IPC分类号: H01L29/786 H01L21/336

    摘要: MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.

    摘要翻译: 提供具有远程触点的MOS结构和用于制造这种MOS结构的方法。 在一个实施例中,一种用于制造MOS结构的方法包括提供半导体层,该半导体层至少部分地被隔离区包围,并且具有杂质掺杂的第一部分。 第一和第二MOS晶体管形成在第一部分内部和第一部分内。 晶体管基本上平行并且在它们之间限定了一个空间。 沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。 通过空间外部的绝缘材料形成触点,使得触点与晶体管电连通。

    TEST STRUCTURE FOR MEASURING ELECTRICAL AND DIMENSIONAL CHARACTERISTICS
    18.
    发明申请
    TEST STRUCTURE FOR MEASURING ELECTRICAL AND DIMENSIONAL CHARACTERISTICS 有权
    测量电气和尺寸特性的测试结构

    公开(公告)号:US20070296444A1

    公开(公告)日:2007-12-27

    申请号:US11426723

    申请日:2006-06-27

    IPC分类号: G01R31/02 G01R31/26

    CPC分类号: G01R31/2884 G01R31/2648

    摘要: A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

    摘要翻译: 测试结构包括第一和第二梳,至少第一对基本节点和第二对​​手指节点。 第一梳子包括从第一基部延伸的第一基部和第一多个指状物。 第二梳子包括从第二基部延伸的第二基部和第二多个指状物。 第一和第二多个手指的至少一部分交错。 第一对基本节点从第一个基地延伸。 所述第二对手指节点从所述第一多个手指的第一手指延伸。

    Test structure and method for measuring the resistance of line-end vias
    19.
    发明授权
    Test structure and method for measuring the resistance of line-end vias 失效
    用于测量线端通孔电阻的测试结构和方法

    公开(公告)号:US07271047B1

    公开(公告)日:2007-09-18

    申请号:US11327641

    申请日:2006-01-06

    IPC分类号: H01L21/8238

    CPC分类号: H01L22/34 H01L22/14

    摘要: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

    摘要翻译: 提供了测试结构及其使用和制造方法。 在一个方面,提供一种测试结构,其包括具有第一端和第二导体的第一导体,第二导​​体具有位于第一端上方的第二端。 第三导体位于第一导体的第一端和第二导体的第二端之间。 第一电极以距离第三导体第一距离的第一导体耦合到第一导体,第二电极以距离第三导体第二距离的方式耦合到第一导体。 第三电极以距离第三导体第三距离的方式耦合到第二导体,并且第四电极在距离第三导体的第四距离处耦合到第二导体。 第一至第四电极提供电压检测抽头,并且第一和第二导体提供电流检测抽头,从该第三导体提供第三导体的电阻。