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    SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR
    13.
    发明申请
    SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
    SOI SiGe-BASE横向双极晶体管晶体管

    公开(公告)号：US20120289018A1

    公开(公告)日：2012-11-15

    申请号：US13556372

    申请日：2012-07-24

    申请人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

    发明人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7317 ,  H01L27/0821 ,  H01L27/1203 ,  H01L29/0808 ,  H01L29/165 ,  H01L29/66265

    摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

    摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。 因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。 基底还可以包括上硅基区和/或下硅基区。 在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。 此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

    SOI SiGe-Base Lateral Bipolar Junction Transistor
    14.
    发明申请
    SOI SiGe-Base Lateral Bipolar Junction Transistor 有权
    SOI SiGe-Base侧向双极结晶体管

    公开(公告)号：US20120139009A1

    公开(公告)日：2012-06-07

    申请号：US12958647

    申请日：2010-12-02

    申请人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

    发明人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

    IPC分类号： H01L29/737 ,  H01L21/8222

    CPC分类号： H01L29/7317 ,  H01L27/0821 ,  H01L27/1203 ,  H01L29/0808 ,  H01L29/165 ,  H01L29/66265

    摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

    摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。 因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。 基底还可以包括上硅基区和/或下硅基区。 在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。 此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

    Monolayer dopant embedded stressor for advanced CMOS
    19.
    发明授权
    Monolayer dopant embedded stressor for advanced CMOS 有权
    单层掺杂剂嵌入式应力器用于高级CMOS

    公开(公告)号：US08236660B2

    公开(公告)日：2012-08-07

    申请号：US12764329

    申请日：2010-04-21

    申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

    摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。