公开(公告)号：US20170125428A1

公开(公告)日：2017-05-04

申请号：US15245540

申请日：2016-08-24

申请人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

发明人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

公开(公告)号：US08987832B2

公开(公告)日：2015-03-24

申请号：US14080823

申请日：2013-11-15

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/088 ,  H01L27/115 ,  H01L27/24 ,  H01L29/423 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。

公开(公告)号：US08822971B2

公开(公告)日：2014-09-02

申请号：US13606789

申请日：2012-09-07

申请人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

发明人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L29/82 ,  H01L21/20

CPC分类号： H01L27/249 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

摘要翻译： 提供半导体存储器件。 该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极 选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

公开(公告)号：US20160163733A1

公开(公告)日：2016-06-09

申请号：US15009040

申请日：2016-01-28

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US20150303209A1

公开(公告)日：2015-10-22

申请号：US14656115

申请日：2015-03-12

申请人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

发明人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

IPC分类号： H01L27/115 ,  H01L27/112

CPC分类号： H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively.

摘要翻译： 提供了形成半导体器件的半导体器件和方法。 半导体器件可以包括设置在单元阵列电路部分下的外围电路部分。 外围电路部分可以驱动单元阵列电路部分。 半导体器件还可以包括连接到外围电路部分的第一导线和连接到电池阵列电路部分的第二导线。 第一导线和第二导线可以具有基本上相同的形状，并且第一导线可以分别与连接区域中的第二导线重叠。

公开(公告)号：US08735860B2

公开(公告)日：2014-05-27

申请号：US13742598

申请日：2013-01-16

申请人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

发明人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L29/02

CPC分类号： H01L45/1206 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.

摘要翻译： 可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线， 沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。 可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。

公开(公告)号：US09343476B2

公开(公告)日：2016-05-17

申请号：US14469611

申请日：2014-08-27

申请人： YuJeong Seo ,  JinTaek Park ,  Youngwoo Park

发明人： YuJeong Seo ,  JinTaek Park ,  Youngwoo Park

IPC分类号： H01L27/115

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.

摘要翻译： 本发明构思提供半导体器件及其制造方法。 根据该方法，重复堆叠具有预定高度和活动孔的子堆叠结构。 因此，可以改善电池分散，并且可以防止在蚀刻工艺中引起的各种误差，例如不开放的误差。 作为通道使用的活性柱的粒径可以使用金属诱导横向结晶法增加或最大化，从而可提高电池电流。 可以控制包括结晶诱导金属的金属硅化物层的形成位置，使得可以根据活性柱中的位置来控制结晶诱导金属的浓度等级。

公开(公告)号：US20130153852A1

公开(公告)日：2013-06-20

申请号：US13690575

申请日：2012-11-30

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L27/249

摘要： A variable resistance memory device comprises a bit line extended in a first direction, a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line in the third direction, a variable resistance layer disposed on a part of the vertical electrode, multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction, and a selection transistor including a first dopant injection region electrically connected to the vertical electrode, and a second dopant injection region electrically connected to the bit line.

摘要翻译： 可变电阻存储器件包括沿第一方向延伸的位线，垂直电极，沿第三方向垂直延伸并且被配置为在第三方向上与位线垂直对准，可变电阻层，设置在垂直方向的一部分上 电极，设置在可变电阻层上并在第三方向上堆叠的多个字线，其中多个字线中的每一个在第二方向上延伸，以及选择晶体管，其包括电连接到垂直电极的第一掺杂剂注入区域，以及 电连接到位线的第二掺杂剂注入区域。

公开(公告)号：US09281019B2

公开(公告)日：2016-03-08

申请号：US14057669

申请日：2013-10-18

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US20140160828A1

公开(公告)日：2014-06-12

申请号：US14057669

申请日：2013-10-18

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： G11C5/06

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。