公开(公告)号：US09183893B2

公开(公告)日：2015-11-10

申请号：US14037547

申请日：2013-09-26

申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

公开(公告)号：US20140306279A1

公开(公告)日：2014-10-16

申请号：US14191542

申请日：2014-02-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L23/00 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

公开(公告)号：US20140151783A1

公开(公告)日：2014-06-05

申请号：US14080823

申请日：2013-11-15

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。

公开(公告)号：US09601204B2

公开(公告)日：2017-03-21

申请号：US14523977

申请日：2014-10-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/11573 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

公开(公告)号：US08987832B2

公开(公告)日：2015-03-24

申请号：US14080823

申请日：2013-11-15

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/088 ,  H01L27/115 ,  H01L27/24 ,  H01L29/423 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。

公开(公告)号：US08822971B2

公开(公告)日：2014-09-02

申请号：US13606789

申请日：2012-09-07

申请人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

发明人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L29/82 ,  H01L21/20

CPC分类号： H01L27/249 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

摘要翻译： 提供半导体存储器件。 该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极 选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

公开(公告)号：US20160163733A1

公开(公告)日：2016-06-09

申请号：US15009040

申请日：2016-01-28

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US09299707B2

公开(公告)日：2016-03-29

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

公开(公告)号：US20150303209A1

公开(公告)日：2015-10-22

申请号：US14656115

申请日：2015-03-12

申请人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

发明人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

IPC分类号： H01L27/115 ,  H01L27/112

CPC分类号： H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively.

摘要翻译： 提供了形成半导体器件的半导体器件和方法。 半导体器件可以包括设置在单元阵列电路部分下的外围电路部分。 外围电路部分可以驱动单元阵列电路部分。 半导体器件还可以包括连接到外围电路部分的第一导线和连接到电池阵列电路部分的第二导线。 第一导线和第二导线可以具有基本上相同的形状，并且第一导线可以分别与连接区域中的第二导线重叠。

公开(公告)号：US08735860B2

公开(公告)日：2014-05-27

申请号：US13742598

申请日：2013-01-16

申请人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

发明人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L29/02

CPC分类号： H01L45/1206 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.

摘要翻译： 可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线， 沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。 可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。