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    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09183893B2

    公开(公告)日：2015-11-10

    申请号：US14037547

    申请日：2013-09-26

    申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    Three-dimensional semiconductor devices with current path selection structure
    4.
    发明授权
    Three-dimensional semiconductor devices with current path selection structure 有权
    具有电流路径选择结构的三维半导体器件

    公开(公告)号：US09299707B2

    公开(公告)日：2016-03-29

    申请号：US14150452

    申请日：2014-01-08

    申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

    CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

    摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

    摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

    Three-dimensional semiconductor devices and methods of fabricating the same
    6.
    发明授权
    Three-dimensional semiconductor devices and methods of fabricating the same 有权
    三维半导体器件及其制造方法

    公开(公告)号：US09019739B2

    公开(公告)日：2015-04-28

    申请号：US14152440

    申请日：2014-01-10

    申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

    发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

    IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

    CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

    摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME 有权
    具有电流路径选择结构的三维半导体器件及其操作方法

    公开(公告)号：US20140197469A1

    公开(公告)日：2014-07-17

    申请号：US14150452

    申请日：2014-01-08

    申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    IPC分类号： H01L27/105

    CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

    摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

    摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

    Non-volatile semiconductor memory device
    9.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07453117B2

    公开(公告)日：2008-11-18

    申请号：US11453796

    申请日：2006-06-16

    申请人： Naoaki Sudo ,  Kohji Kanamori

    发明人： Naoaki Sudo ,  Kohji Kanamori

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7887 ,  G11C16/0441 ,  G11C16/0491 ,  G11C16/28 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.

    摘要翻译： 实现高速可靠的读取操作。 单位电池由设置在第一区域中的选择栅极3和介于其间的绝缘膜2的基板1构成，设置在与第一区域相邻的第二区域中的浮置栅极6a与介于其间的绝缘膜5 设置在与第二区域相邻的第三区域和衬底的表面上的扩散区域7a，以及设置在浮置栅极6a的顶部上的绝缘膜8的控制栅极11。 使用对应的第一单元单元和第二单元单元存储每个数据位。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07411838B2

    公开(公告)日：2008-08-12

    申请号：US11700184

    申请日：2007-01-31

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11524 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

    摘要： A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the voltage applied to the selection gate SG0 to the selection gate SG1, and a positive voltage to the local bit line LB2, the drive circuit 22 controls so that electrons are selectively drawn out of a floating gate FG3 to the local bit line LB2 by F-N tunneling during writing operation. Sufficient operation margin is obtained even when memory cells are miniaturized.

    摘要翻译： 驱动电路22控制施加到基板1，选择栅极SG0和SG1，局部位线LB2和控制栅极CGn的电压。 通过分别对控制栅极CGn施加负电压，向选择栅极SG0施加正电压，低于施加到选择栅极SG0的电压至选择栅极SG1的电压，以及对该局部位置的正电压 线路LB2，驱动电路22进行控制，使得在写入操作期间，通过FN隧穿，电子被选择性地从浮动栅极FG3拉出到局部位线LB 2。 即使存储单元小型化，也能获得足够的操作余量。