公开(公告)号：US07937601B2

公开(公告)日：2011-05-03

申请号：US12535814

申请日：2009-08-05

申请人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kilkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

发明人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kilkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

IPC分类号： G06F1/30 ,  H03K19/173

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

摘要翻译： 一种可编程片上系统集成电路装置，包括可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块。 可编程互连架构包括可编程元件和互连导体。 可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得 可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

公开(公告)号：US07872497B2

公开(公告)日：2011-01-18

申请号：US12645863

申请日：2009-12-23

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/173 ,  G06F7/42 ,  G06F15/00

CPC分类号： G06F7/506 ,  H03K19/17728

摘要： A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

摘要翻译： 描述了用于集群现场可编程门阵列架构的快速，灵活的携带方案。 每个集群具有集群进位输入节点，集群进位输出节点，具有耦合到集群进位输出节点的输出的集群进位输出电路，耦合到集群进位输入节点的第一输入和第二输入和多个 每个逻辑模块包括耦合到进位电路的逻辑功能发生器电路。 逻辑模块以集群进位输入节点和集群携带输出电路的第二输入之间的串联进位装置耦合，使得算术逻辑电路的最低有效位可以可编程地置于任何逻辑模块中。

公开(公告)号：US20100244894A1

公开(公告)日：2010-09-30

申请号：US12794279

申请日：2010-06-04

申请人： Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

发明人： Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/17768 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

摘要翻译： 增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。 电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

公开(公告)号：US20100038697A1

公开(公告)日：2010-02-18

申请号：US12370828

申请日：2009-02-13

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US07663400B1

公开(公告)日：2010-02-16

申请号：US11962922

申请日：2007-12-21

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/173 ,  G06F7/42 ,  G06F15/00

CPC分类号： G06F7/506 ,  H03K19/17728

摘要： A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

摘要翻译： 描述了用于集群现场可编程门阵列架构的快速，灵活的携带方案。 每个集群具有集群进位输入节点，集群进位输出节点，具有耦合到集群进位输出节点的输出的集群进位输出电路，耦合到集群进位输入节点的第一输入和第二输入和多个 每个逻辑模块包括耦合到进位电路的逻辑功能发生器电路。 逻辑模块以集群携带输入节点和集群携带输出电路的第二输入之间的串联进位布置耦合，使得算术逻辑电路的最低有效位可以可编程地置于任何逻辑模块中。

公开(公告)号：US07516303B2

公开(公告)日：2009-04-07

申请号：US11187068

申请日：2005-07-22

申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F15/7842 ,  G06F15/7867

摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

公开(公告)号：US07432733B1

公开(公告)日：2008-10-07

申请号：US11531375

申请日：2006-09-13

申请人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

发明人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

摘要翻译： 具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。 逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。 第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构 组件。

公开(公告)号：US07403411B1

公开(公告)日：2008-07-22

申请号：US11484243

申请日：2006-07-10

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.

摘要翻译： 一种用于为耐辐射静态随机存取存储器（SRAM）提供消旋电路的方法，包括：提供具有多个配置位的配置存储器; 将读和写电路耦合到配置存储器，用于配置多个配置位; 将辐射硬锁存器耦合到可编程元件，所述辐射硬锁存器控制所述可编程元件; 以及当所述写电路写入所述多个配置位中的至少一个配置位时，提供将所述多个配置位中的至少一个耦合到所述辐射硬锁存器的接口。

公开(公告)号：US07385419B1

公开(公告)日：2008-06-10

申请号：US11677432

申请日：2007-02-21

申请人： William C. Plants ,  Arunangshu Kundu

发明人： William C. Plants ,  Arunangshu Kundu

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/1776 ,  H03K19/17744

摘要： A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

摘要翻译： 具有多个输入/输出焊盘的现场可编程门阵列架构。 该架构包括：多个逻辑簇; 多个输入/输出群集; 多个输入/输出缓冲器; 多个专用输入/输出先进先出存储块，专用输入/输出先进先出存储块具有耦合到多个输入/输出存储器中的一个的先进先出存储器， 输出垫; 可编程地耦合到所述多个专用输入/输出先入/先出存储块的输入/输出块控制器; 以及可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连架构，其中专用输入/输出先入先出存储器块可编程地耦合在输入/输出缓冲器和输入/ 输出集群。

公开(公告)号：US07288957B2

公开(公告)日：2007-10-30

申请号：US11617559

申请日：2006-12-28

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/003

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。