摘要:
An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要:
Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要:
Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要:
A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要:
A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要:
A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要:
A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.
摘要:
A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
摘要:
A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要:
Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.