Microelectronic substrate having removable edge extension element
    11.
    发明授权
    Microelectronic substrate having removable edge extension element 有权
    具有可移除边缘延伸元件的微电子基板

    公开(公告)号:US08946866B2

    公开(公告)日:2015-02-03

    申请号:US13490239

    申请日:2012-06-06

    IPC分类号: H01L29/06 G03F7/20

    摘要: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

    摘要翻译: 提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。 这种物品包括具有前表面,与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。 前表面是物品的主要表面。 具有前表面,后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。 以这种方式,形成连续表面,其包括边缘延伸元件的前表面,该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸,连续表面基本上共平面且平坦, 周缘连接到内边缘。

    Formation of the dielectric cap layer for a replacement gate structure
    13.
    发明授权
    Formation of the dielectric cap layer for a replacement gate structure 有权
    用于替代栅极结构的电介质盖层的形成

    公开(公告)号:US08772168B2

    公开(公告)日:2014-07-08

    申请号:US13353708

    申请日:2012-01-19

    IPC分类号: H01L21/311

    摘要: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.

    摘要翻译: 通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。 实施例包括在衬底上形成替代的栅极结构,所述替换的栅极结构包括具有空腔的ILD,在ILD的顶表面上的第一金属和衬里的空腔,以及在第一金属上填充空腔的第二金属, 平面化第一和第二金属,在第二金属上形成氧化物,去除氧化物,使空腔中的第一和第二金属凹陷,形成凹陷,并用电介质材料填充凹槽。 实施例还包括具有垂直侧壁,梯形形状,T形或Y形的电介质盖。

    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
    14.
    发明申请
    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
    通过掩蔽和反应离子蚀刻(RIE)技术的超耐性

    公开(公告)号:US20140061930A1

    公开(公告)日:2014-03-06

    申请号:US13604660

    申请日:2012-09-06

    IPC分类号: H01L23/48 H01L21/768

    摘要: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

    摘要翻译: 提供了一种方法,其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底,其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度,并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

    Electrical fuse structure and method of fabricating same
    15.
    发明授权
    Electrical fuse structure and method of fabricating same 有权
    电熔丝结构及其制造方法

    公开(公告)号:US08609534B2

    公开(公告)日:2013-12-17

    申请号:US12890941

    申请日:2010-09-27

    IPC分类号: H01L21/4763

    摘要: A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

    摘要翻译: 使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。 双镶嵌结构包括图案化电介质材料,其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。 通孔开口位于顶部并连接到金属层。 双镶嵌结构还包括线路开口和通孔开口内的导电特征。 电介质间隔物也存在于线路开口和通孔开口内。 介电间隔物存在于图案化电介质材料的垂直侧壁上,并将导电特征与图案化电介质材料分开。 在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。 因此,提供了节省空间的高编程效率电熔丝。

    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME
    16.
    发明申请
    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
    双重对等双向对联方案

    公开(公告)号:US20130328208A1

    公开(公告)日:2013-12-12

    申请号:US13490542

    申请日:2012-06-07

    IPC分类号: H01L23/48 H01L21/28

    摘要: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    摘要翻译: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部,以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构,其包括沿着两个独立的水平方向横向限制的通孔结构。

    Multi-exposure lithography employing a single anti-reflective coating layer
    18.
    发明授权
    Multi-exposure lithography employing a single anti-reflective coating layer 失效
    使用单个抗反射涂层的多曝光光刻

    公开(公告)号:US08507187B2

    公开(公告)日:2013-08-13

    申请号:US12169888

    申请日:2008-07-09

    IPC分类号: G03F7/20

    摘要: A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.

    摘要翻译: 将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。 第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。 施加第二光致抗蚀剂并将其图案化成具有接近最小特​​征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。 第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。 复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

    Metal Alloy Cap Integration
    19.
    发明申请
    Metal Alloy Cap Integration 审中-公开
    金属合金盖整合

    公开(公告)号:US20130112462A1

    公开(公告)日:2013-05-09

    申请号:US13290557

    申请日:2011-11-07

    IPC分类号: H05K1/09 H05K3/00

    摘要: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.

    摘要翻译: 包括金属合金覆盖层的金属互连结构及其制造方法。 互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。 金属合金覆盖材料沉积在回流铜表面上,并且不物理地与互连特征的侧壁接触。 因此,互连结构中的残余合金元素的电阻率冲击降低。 也就是说,在金属互连结构的特征内部存在合金元素的减少。 金属互连结构包括具有凹陷线的介电层,侧壁上的衬垫材料,铜材料,合金盖和覆盖层。