公开(公告)号：US06580635B1

公开(公告)日：2003-06-17

申请号：US10133946

申请日：2002-04-25

申请人： Todd W. Mellinger ,  Jonathan E. Lachman ,  John Wuu

发明人： Todd W. Mellinger ,  Jonathan E. Lachman ,  John Wuu

IPC分类号： G11C1140

CPC分类号： G11C7/12 ,  G11C7/18

摘要： During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is used during the read operation to relay data from one part of the split bitline to the other. A weak pullup path is also provided to hold the non-driven end of the line in a stable condition. During non-read operations, the two sections of bitline are electrically connected.

摘要翻译： 在一列RAM单元的读操作期间，位线被电分为两部分。 这就降低了RAM单元本身需要放电的电容。 在读取操作期间使用缓冲器将数据从分割位线的一部分中继到另一部分。 还提供弱上拉路径以将线的非驱动端保持在稳定状态。 在非读取操作期间，位线的两个部分电连接。

公开(公告)号：US20130155795A1

公开(公告)日：2013-06-20

申请号：US13329580

申请日：2011-12-19

申请人： Mayank Gupta ,  John Wuu

发明人： Mayank Gupta ,  John Wuu

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/412 ,  H01L27/11

摘要： A method for recovering failed bit cells in an integrated circuit memory is disclosed. In one embodiment, the method includes stress testing an integrated circuit having a memory, wherein the memory includes a plurality of bit cells. The method further includes holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells.

摘要翻译： 公开了一种用于恢复集成电路存储器中的故障比特单元的方法。 在一个实施例中，该方法包括对具有存储器的集成电路进行压力测试，其中存储器包括多个位单元。 所述方法还包括将所述多个比特单元中的所选择的一个比特单元的至少一个内部节点保持在第一预定状态，持续足以引起所述多个比特单元中所选择的一个比特单元中的晶体管的阈值电压的偏移 。

公开(公告)号：US08464130B2

公开(公告)日：2013-06-11

申请号：US12330012

申请日：2008-12-08

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

摘要翻译： 公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

公开(公告)号：US20100002502A1

公开(公告)日：2010-01-07

申请号：US12167821

申请日：2008-07-03

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C15/04 ,  G06F12/0864 ,  G06F12/0895 ,  G11C11/39

摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

公开(公告)号：US07133319B2

公开(公告)日：2006-11-07

申请号：US10600878

申请日：2003-06-20

申请人： John Wuu ,  Blaine Stackhouse ,  Donald R. Weiss

发明人： John Wuu ,  Blaine Stackhouse ,  Donald R. Weiss

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/41 ,  G11C29/12 ,  G11C29/12005

摘要： The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

摘要翻译： 本发明采用具有可选择量值的偏置电压来偏置静态随机存取存储器（SRAM）阵列的写入驱动器中的弱写入下拉晶体管。 可编程弱写入测试模式（PWWTM）偏置发生器包括当WWTM不活动时，默认模式下的逻辑高电平的输出信号。 当WWTM有效时，发生器输出信号是具有可选择量值的偏置电压。 当发电机输出连接到负载（如SRAM阵列的写入驱动器）时，主动保持默认模式逻辑高电平。 支持WWTM的SRAM系统包括PWWTM偏置发生器。 驱动配备有WWTM的SRAM的方法包括在默认模式和WWTM中产生并施加输出信号到SRAM阵列写入驱动器的弱写入下拉晶体管的栅极。

公开(公告)号：US06366526B2

公开(公告)日：2002-04-02

申请号：US09790132

申请日：2001-02-21

申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C11/418

摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder accepts an addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder also outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include logic to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any single memory cell in the SRAM cell for reading or writing specific logical states.

摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以可能的最大速度来优化存储器单元的阵列密度，以便对存储单元进行寻址和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器接受寻址输入并输出用于选择SRAM阵列中存储单元的单独列的信号。 全局解码器还输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的逻辑。 因此，全局解码器能够选择SRAM单元中的任何单个存储器单元用于读取或写入特定的逻辑状态。

公开(公告)号：US06282143B1

公开(公告)日：2001-08-28

申请号：US09084689

申请日：1998-05-26

申请人： Kevin Zhang ,  John Wuu

发明人： Kevin Zhang ,  John Wuu

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： A static random-access memory (SRAM) comprises multi-port storage cells with built-in column-interleave selection circuitry which allow a storage cell to be written to via a plurality of different write paths. Column selects are built into each storage cell by adding an additional isolating switch between the storage node of the storage cell and the bitline of a particular write path in order to prevent a cell write from affecting other storage cells connected to the same wordline in the same interleaved array. The write data bus corresponding to each write path for all interleaved cells are shared by all storage cells in a common interleave group, and each adjacent pair of storage cells in a common row share bitlines coupled to the common data bus, resulting in smaller number of required bitlines.

摘要翻译： 静态随机存取存储器（SRAM）包括具有内置列交错选择电路的多端口存储单元，其允许经由多个不同写入路径写入存储单元。 通过在存储单元的存储节点和特定写入路径的位线之间添加一个额外的隔离开关，可以在每个存储单元中内置列选择，以防止单元写入影响连接到同一字线的其他存储单元 交错数组。 与所有交织单元的每个写入路径对应的写数据总线由公共交错组中的所有存储单元共享，并且公共行中的每个相邻的存储单元对共享与公共数据总线相连的位线，导致较小数量的 需要的位线

公开(公告)号：US06243287B1

公开(公告)日：2001-06-05

申请号：US09492510

申请日：2000-01-27

申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

IPC分类号： G11C1100

CPC分类号： G11C8/10 ,  G11C11/418

摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder includes a first logic block that accepts addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder includes a second logic block that accepts addressing input and outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include a third logic block to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any signal memory cell in the SRAM cell for reading or writing specific logical states.

摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以阵列中的存储器单元的密度优化，以最大速度寻址存储器单元以进行读取和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器包括第一逻辑块，其接受寻址输入并输出用于选择SRAM阵列中的存储单元的单独列的信号。 全局解码器包括第二逻辑块，其接受寻址输入并输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的第三逻辑块。 因此，全局解码器能够选择SRAM单元中的任何信号存储单元用于读取或写入特定的逻辑状态。

公开(公告)号：US06192001B1

公开(公告)日：2001-02-20

申请号：US09510287

申请日：2000-02-21

申请人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

发明人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

IPC分类号： G11C810

CPC分类号： G11C11/419

摘要： The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

摘要翻译： 本发明将WWTM电路与写驱动器电路集成，该驱动器电路是任何常规SRAM设计的固有部分。 因此，提供了用于将数据写入并弱写入测试存储器单元的电路。 在一个实施例中，电路包括具有用于在存储器单元处施加写入或弱写入输出信号的输出的写入驱动器。 写驱动器具有第一和第二可选操作模式。 在第一模式中，写入驱动器被设置为从输出端施加弱写入输出信号，以对单元执行弱写入测试。 在第二模式中，写入驱动器被设置为施加足够强的正常写入输出信号，以便当数据值健康时将数据值写入单元。

公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.