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11.发明授权Circuits for preventing breakdown of low-voltage device inputs during high voltage antifuse programming 失效用于在高电压反熔丝编程期间防止低压设备输入故障的电路
公开(公告)号：US5095228A
公开(公告)日：1992-03-10
申请号：US687980
申请日：1991-04-19
IPC分类号： H01L21/82 , G11C17/18 , H01L21/822 , H01L27/04 , H03K17/10 , H03K19/003
CPC分类号： H03K17/102 , G11C17/18 , H03K19/00315
摘要： A circuit for isolating a first low-voltage circuit mode from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes a novel two input NAND gate having one input structure configured from high voltage devices connected to the second circuit node. The other input of the NAND gate is a control input for the isolation device and is connected to a low-voltage logic signal which is high when the signal from the high programming voltage node is to be passed through to the low-voltage node and low when the low-voltage node is to be isolated from the high programming voltage node. The output of the NAND gate is connected to the first low-voltage circuit node.
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公开(公告)号：US4910417A
公开(公告)日：1990-03-20
申请号：US293645
申请日：1989-01-05
IPC分类号： G01R31/3185 , H03K19/177 , H03K19/094
CPC分类号： H03K19/17728 , G01R31/318516 , H03K19/17704
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conductive to custom circuit design.
摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 布线通道包括通过常开的可编程元件连接的布线段，所述可编程元件位于要连接的任何两个段的交点处。 可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。 通用功能模块可以被配置为实现流行的逻辑功能，并且具有对定制电路设计有导通性的物理布局。
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公开(公告)号：US07932745B2
公开(公告)日：2011-04-26
申请号：US12879306
申请日：2010-09-10
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译： 公开了一种用于现场可编程门阵列集成电路器件的触发器。 触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号 时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。
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公开(公告)号：US20100327906A1
公开(公告)日：2010-12-30
申请号：US12879306
申请日：2010-09-10
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译： 公开了一种用于现场可编程门阵列集成电路器件的触发器。 触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号 时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。
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公开(公告)号：US20100060311A1
公开(公告)日：2010-03-11
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
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公开(公告)号：US20090051050A1
公开(公告)日：2009-02-26
申请号：US11844881
申请日：2007-08-24
IPC分类号： H01L23/49
CPC分类号： H01L23/5286 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06179 , H01L2224/48091 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die.
摘要翻译： 集成电路管芯具有围绕其周边设置的多个I / O单元，每个I / O单元具有I / O焊盘。 第一组I / O单元设置在远离模具角部的位置处的管芯周边处，第一组I / O单元中的每一个具有设置在其上的I / O焊盘，并且间隔开第一距离 模具的周边。 第二组I / O单元设置在离芯片的角部的位置处的管芯周边处，第二组I / O单元中的每一个具有设置在其上的间隔开的距离， 模具的周边大于第一距离，该距离随着每个I / O单元与模具角落的接近程度的增加而增加。
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公开(公告)号：US5191241A
公开(公告)日：1993-03-02
申请号：US899729
申请日：1992-06-17
IPC分类号： H01L23/525 , H01L23/528
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
摘要翻译： 用户可配置电路架构包括布置在半导体衬底内的功能电路模块的二维阵列。 设置在半导体衬底上方并与半导体衬底绝缘的第一互连层包含多个导体并且用于功能电路模块内的内部连接。 设置在第一互连层之上并与第一互连层绝缘的第二互连层包含沿第一方向运行的多个导体的导体轨道，并用于互连功能电路模块的输入和输出。 设置在第二互连层之上并与第二互连层绝缘的第三互连层包含沿第二方向延伸的导体的多个分段轨迹，导体中的一些导体与第二互连层中的导体中的一个段形成相交;以及 用于互连功能电路模块输入和输出以实现所需的应用。 多个用户可配置的互连元件直接放置在第二和第三互连层中的分段导体的选定段的交叉处的第二和第三互连层之间。 更多用户可配置的互连元件位于第二和第三互连层中的分段导体的相邻段之间。 位于功能电路模块之间的半导体衬底中的通过晶体管连接在第二和第三互连层中的相邻段之间以及第二和第三互连层中的选定交叉段之间。
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公开(公告)号：US5017813A
公开(公告)日：1991-05-21
申请号：US522389
申请日：1990-05-11
IPC分类号： G06F3/00 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/01759
摘要： An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer/level shifter for translating the logic signals from the outside world to CMOS compatible levels. The input buffer may be placed in a high impedance state by a control signal applied to a control input. The output of the input buffer/level shifter is connected to a first data input of a two-input multiplexer. The output of the two-input multiplexer is connected to an internal bus and to the second data input of the two-input multiplexer. The select input of the two-input multiplexer is connected to a control signal, preferably to the same control signal used to enable the input buffer/level shifter. The output section of the input/output module section of the present invention includes a two-input multiplexer having a first input connected to an internal data bus, and its output fed back to its second data input. Its select input is driven from a control signal. The output of the two-input multiplexer is also connected to the input of an HCT buffer. The output of the HCT buffer is connected to an I/O pad of the integrated circuit, which may be the same pad to which the input section is connected. The slew input of the HCT buffer is driven from a signal enabling slow or fast rise times. The enable input of the HCT buffer is driven from an enable signal which may be derived from other logic signals.
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公开(公告)号：US20100156457A1
公开(公告)日：2010-06-24
申请号：US12340358
申请日：2008-12-19
IPC分类号： H03K19/177 , H03K19/0175
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。
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公开(公告)号：US07430137B2
公开(公告)日：2008-09-30
申请号：US11868694
申请日：2007-10-08
IPC分类号： G11C16/02 , G11C5/02 , G11C5/06 , G06F7/38 , H03K19/173 , H03K19/177 , H03K19/94
CPC分类号： H03K19/1776 , G11C16/0441 , H03K19/17736 , H03K19/1778
摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.
摘要翻译： 非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。 第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。 第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。 第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极 电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。
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