公开(公告)号：US20070190681A1

公开(公告)日：2007-08-16

申请号：US11352724

申请日：2006-02-13

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/14649 ,  H01L27/14609 ,  H01L27/14689

摘要： A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×1016 to about 5×1018 cm−3.

摘要翻译： 提供了一种用于在绝缘体上硅（SOI）衬底上形成近红外（NIR）有源像素传感器阵列的方法。 该方法形成包括高电阻第一Si衬底和中度掺杂的第一Si层的第一晶片，并且形成包括第一氧化硅层和第二Si层的第二晶片。 该方法将第一晶片连接到第二晶片，形成SOI衬底。 然后，形成具有延伸到第一Si衬底中的p-n结空间电荷区域的二极管。 在第二Si层中形成薄膜晶体管（TFT），并且在TFT和二极管之间形成互连。 例如，第一Si衬底可以具有大于100欧姆 - 厘米的电阻率，并且第一Si层可以具有在约1×10 16至约5×10 18范围内的掺杂剂浓度， / SUP> cm 3 -3。

公开(公告)号：US20070099329A1

公开(公告)日：2007-05-03

申请号：US11260955

申请日：2005-10-27

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1808 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02647 ,  H01L31/105 ,  Y02E10/50

摘要： A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and in the contact holes; growing an intrinsic germanium layer on the epitaxial germanium layer and any exposed silicon oxide layer; growing a germanium layer of a second type on the intrinsic germanium layer and any exposed silicon oxide layer; depositing a layer of covering material take from the group of materials consisting of polysilicon, polysilicon-germanium and In2O3—SnO2; and etching the covering material to form individual sensing elements.

摘要翻译： 制造锗光电检测器的方法包括制备硅衬底; 沉积和平坦化氧化硅层; 在氧化硅层中形成与底层硅衬底连通的接触孔; 在氧化硅层和接触孔中生长第一类型的外延锗层; 在外延锗层和任何暴露的氧化硅层上生长内在的锗层; 在内部锗层和任何暴露的氧化硅层上生长第二类型的锗层; 沉积一层覆盖材料取自由多晶硅，多晶硅 - 锗和In 2 N 3 O 3 -SnO 2 2组成的材料组。 并蚀刻覆盖材料以形成单独的感测元件。

公开(公告)号：US20060194357A1

公开(公告)日：2006-08-31

申请号：US11240969

申请日：2005-09-30

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L31/1126 ,  C30B19/00 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02623 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/7624 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/78 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547

摘要： A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

摘要翻译： 提供了高密度锗（Ge）绝缘体（GOI）光电二极管阵列和相应的制造方法。 该方法包括：形成像素驱动器nMOST器件的阵列，每个器件具有以第一取向连接到行线的栅极，第一源极/漏极（S / D）区域和连接到Vdd的第二S / D区域 ; 如下形成每个像素的P-I-N Ge二极管：形成n +区; 形成覆盖n +区域的本征Ge区域; 在本征Ge中形成p +结; 并隔离P-I-N Ge二极管; 并且以与第一取向正交的第二取向形成铟锡氧化物（ITO）柱，覆盖P-I-N Ge二极管。

公开(公告)号：US20060110844A1

公开(公告)日：2006-05-25

申请号：US10993533

申请日：2004-11-19

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1804 ,  H01L21/187 ,  H01L21/76254 ,  H01L27/1443 ,  H01L31/02327 ,  H01L31/105 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

摘要翻译： 制造薄膜锗光电探测器的方法包括制备硅衬底; 在硅衬底上制造CMOS器件; 制备锗衬底; 准备每个基板的表面以进行接合; 将锗衬底结合到具有CMOS的硅衬底以形成结合结构; 从结合结构去除锗衬底的一部分; 在锗衬底中形成PIN二极管; 通过蚀刻去除锗层的一部分; 并完成锗光电检测器。

公开(公告)号：US20060073708A1

公开(公告)日：2006-04-06

申请号：US11284326

申请日：2005-11-21

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

IPC分类号： H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

公开(公告)号：US20050151134A1

公开(公告)日：2005-07-14

申请号：US11073185

申请日：2005-03-03

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Douglas Tweet ,  Jer-shen Maa

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法包括：形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成第二层弛豫的SiGe，覆盖衬底并与第一层SiGe相邻，厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于所述第一SiGe层和所述第二SiGe层之间的浅沟槽隔离区域; 在衬底和上覆的第一层SiGe中形成n阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

公开(公告)号：US20070298588A1

公开(公告)日：2007-12-27

申请号：US11891502

申请日：2007-08-10

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/301

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68368 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

摘要翻译： 通过层转移制造硅塑料层的方法包括在硅衬底上沉积SiGe层; 沉积一层硅; 将氢离子注入到硅衬底中; 将玻璃基板结合到硅层; 分裂晶片; 去除所述硅层和所述SiGe层的一部分; 在玻璃上硅晶片的硅侧沉积电介质; 施加粘合剂并将塑料基板粘合到硅玻璃晶片的硅侧; 从接合的硅玻璃晶片的玻璃面上移除玻璃以形成硅 - 硅晶片; 并在塑料硅胶上完成所需的IC器件。 可以通过重复本发明方法的最后几个步骤，根据本发明的方法制造多层结构。

公开(公告)号：US20070099315A1

公开(公告)日：2007-05-03

申请号：US11353802

申请日：2006-02-13

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1808 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02647 ,  H01L31/105 ,  Y02E10/50

摘要： A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

摘要翻译： 制造锗光电检测器的方法包括制备硅衬底晶片并在硅衬底上沉积并平面化氧化硅层。 在氧化硅层中形成接触孔。 在氧化硅层和接触孔中生长N +外延锗层。 N +锗层由ELO形成。 结构平滑和变薄。 内在锗层生长在N +外延锗层上。 在本征锗层上形成P +锗层，并沉积氧化硅外涂层。 通过氧化硅外涂层向P +锗层打开窗口。 一层导电材料沉积在氧化硅外涂层和其中的窗口中。 蚀刻导电材料以形成各个感测元件。

公开(公告)号：US20060246606A1

公开(公告)日：2006-11-02

申请号：US11120385

申请日：2005-05-02

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Wei-Wei Zhuang

IPC分类号： H01L21/8234

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

摘要翻译： 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

公开(公告)号：US20060113522A1

公开(公告)日：2006-06-01

申请号：US11327092

申请日：2006-01-06

申请人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687

摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

摘要翻译： 公开了一种应变硅finFET器件，其具有双栅极finFET结构中的应变硅鳍通道。 所公开的finFET器件是由用于抑制短沟道效应和增强驱动电流的自对准双栅极控制的硅鳍通道组成的双栅极MOSFET。 所公开的finFET器件的硅鳍通道是应变硅鳍通道，包括沉积在具有不同晶格常数的种子鳍上的应变硅层，例如沉积在硅锗晶种鳍上的硅层或碳掺杂硅 层沉积在硅种子翅片上。 除了在finFET器件中固有的短沟道效应降低特性之外，硅层和种子鳍之间的晶格失配在所公开的finFET器件中产生应变硅鳍通道，以改善空穴和电子迁移率增强。