公开(公告)号：US20070290288A1

公开(公告)日：2007-12-20

申请号：US11894938

申请日：2007-08-22

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L31/10

CPC分类号： H01L31/1136

摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

摘要翻译： 提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。 该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。 在一个方面，第二S / D区域具有比第一S / D长度更长的长度。 光吸收阈值偏置区域位于第二S / D区域的下方。 或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

公开(公告)号：US20060281232A1

公开(公告)日：2006-12-14

申请号：US11149891

申请日：2005-06-10

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78684

摘要： A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.

摘要翻译： 制造硅 - 锗CMOS的方法包括制备硅衬底晶片; 在硅衬底晶片上沉积绝缘层; 图案化和蚀刻绝缘层; 在所述绝缘层和所述硅衬底晶片的至少一部分上沉积多晶锗层; 图案化和蚀刻多晶锗; 用绝缘材料封装多晶锗; 在足以熔化多晶锗的温度下快速热退火晶片; 冷却晶片以促进多晶锗的液相外延，从而形成单晶锗层; 并完成CMOS设备。

公开(公告)号：US20060194415A1

公开(公告)日：2006-08-31

申请号：US11069422

申请日：2005-02-28

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L27/14634 ,  H01L27/14649 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.

摘要翻译： 制造用于CMOS成像器的锗红外传感器的方法包括制备施主晶片，其包括：离子注入到硅晶片中以形成P +硅层; 在P +硅层上生长外延锗层，形成硅 - 锗界面; 循环退火; 以及将氢离子注入至少与P +硅层一样深的深度以形成缺陷层; 制备处理晶片，包括：在硅衬底上制造CMOS集成电路; 沉积难熔金属层; 处理供体晶片的表面和用于结合的处理晶片; 结合处理晶片和施主晶片以形成结合结构; 沿着缺陷层分离粘结结构; 在锗层上沉积一层氧化铟锡; 完成IR传感器。

公开(公告)号：US20050070115A1

公开(公告)日：2005-03-31

申请号：US10677005

申请日：2003-09-30

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/20 ,  H01L21/302 ,  H01L21/461 ,  H01L21/762

CPC分类号： H01L21/76254

摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.

摘要翻译： 在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

公开(公告)号：US20070170536A1

公开(公告)日：2007-07-26

申请号：US11339011

申请日：2006-01-25

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L31/00

CPC分类号： H01L31/1055 ,  H01L31/1808 ,  H01L31/1872 ,  Y02E10/50

摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.

摘要翻译： 提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。 该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。 然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。 在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。 在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

公开(公告)号：US20070141744A1

公开(公告)日：2007-06-21

申请号：US11312967

申请日：2005-12-19

申请人： Jong-Jan Lee ,  Douglas Tweet ,  Jer-Shen Maa ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Douglas Tweet ,  Jer-Shen Maa ,  Sheng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L31/105 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S438/933

摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

摘要翻译： 制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

公开(公告)号：US20070001163A1

公开(公告)日：2007-01-04

申请号：US11174035

申请日：2005-07-01

申请人： Jong-Jan Lee ,  Sheng Hsu ,  Jer-Shen Maa ,  Douglas Tweet

发明人： Jong-Jan Lee ,  Sheng Hsu ,  Jer-Shen Maa ,  Douglas Tweet

IPC分类号： H01L31/00

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

公开(公告)号：US20060189151A1

公开(公告)日：2006-08-24

申请号：US11384121

申请日：2006-03-17

申请人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

发明人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L31/035281 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/101 ,  H01L31/1812 ,  Y02E10/50

摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

摘要翻译： 提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。 该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。 在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。 然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

公开(公告)号：US20060189111A1

公开(公告)日：2006-08-24

申请号：US11060878

申请日：2005-02-18

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78621

摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

摘要翻译： 在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

公开(公告)号：US20070298588A1

公开(公告)日：2007-12-27

申请号：US11891502

申请日：2007-08-10

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/301

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68368 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

摘要翻译： 通过层转移制造硅塑料层的方法包括在硅衬底上沉积SiGe层; 沉积一层硅; 将氢离子注入到硅衬底中; 将玻璃基板结合到硅层; 分裂晶片; 去除所述硅层和所述SiGe层的一部分; 在玻璃上硅晶片的硅侧沉积电介质; 施加粘合剂并将塑料基板粘合到硅玻璃晶片的硅侧; 从接合的硅玻璃晶片的玻璃面上移除玻璃以形成硅 - 硅晶片; 并在塑料硅胶上完成所需的IC器件。 可以通过重复本发明方法的最后几个步骤，根据本发明的方法制造多层结构。