公开(公告)号：US07904868B2

公开(公告)日：2011-03-08

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20100210043A1

公开(公告)日：2010-08-19

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US20080308940A1

公开(公告)日：2008-12-18

申请号：US12198196

申请日：2008-08-26

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07453151B2

公开(公告)日：2008-11-18

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L29/80

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07384824B2

公开(公告)日：2008-06-10

申请号：US11362680

申请日：2006-02-27

申请人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

发明人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

IPC分类号： H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

摘要翻译： 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的电介质层。 熔丝连接在电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。

公开(公告)号：US5533197A

公开(公告)日：1996-07-02

申请号：US327151

申请日：1994-10-21

申请人： David E. Moran ,  Timothy J. O'Gorman ,  Kimball M. Watson

发明人： David E. Moran ,  Timothy J. O'Gorman ,  Kimball M. Watson

IPC分类号： G01R31/26 ,  G01R31/28 ,  G06F11/34 ,  G06F11/00

CPC分类号： G01R31/2858 ,  G01R31/2648 ,  G06F11/34 ,  G01R31/287

摘要： A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions. A timing equation is evaluated using distinctly identified components of the propagation delay degradation caused by electromigration and hot electron effects, to assess the toleration of the microprocessor to electromigration and hot electron induced propagation delay degradation.

摘要翻译： 提供了一种评估微机对由电迁移效应和热电子效应引起的传播时间劣化的容限的方法。 互连电阻（IR）劣化和漏极电流（DC）劣化的参考值在标称制造工艺和微处理器使用寿命应用条件下进行计算。 这些结果可以列出多个输出驱动器负载电容。 通过对实际测试条件分别缩放参考IR和DC降级值来计算测试IR降解和测试DC降解值。 在过程和终身环境条件下计算电迁移和电子电子效应引起的电路传播时间和传播延迟劣化。 使用由电迁移和热电子效应引起的传播延迟劣化的明确识别的分量来评估时序方程，以评估微处理器对电迁移和热电子诱导传播延迟退化的容忍度。

公开(公告)号：US08686478B2

公开(公告)日：2014-04-01

申请号：US13295392

申请日：2011-11-14

申请人： Benjamin T. Voegeli ,  Kimball M. Watson

发明人： Benjamin T. Voegeli ,  Kimball M. Watson

IPC分类号： H01L21/336

CPC分类号： H01L27/0635 ,  H01L21/8249 ,  H01L27/0802

摘要： Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.

摘要翻译： 通过在与电阻器相邻的俘获电荷区域中使用俘获电荷来改变电阻器和电阻器的电阻来对扩散电阻器进行电气编程的方法。 在一个实施例中，一种方法包括在衬底中形成扩散电阻器; 形成与扩散电阻相邻的俘获电荷区; 以及通过控制捕获的电荷区域中的捕获电荷来调节扩散电阻器的电阻。

公开(公告)号：US20090253239A1

公开(公告)日：2009-10-08

申请号：US12062262

申请日：2008-04-03

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

IPC分类号： H01L21/331

CPC分类号： H01L29/41708 ,  H01L27/0629 ,  H01L27/0658 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/78

摘要： A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.

摘要翻译： 一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。 可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。 该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。

公开(公告)号：US07064409B2

公开(公告)日：2006-06-20

申请号：US10605885

申请日：2003-11-04

申请人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

发明人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

摘要翻译： 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝连接在第一电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。

公开(公告)号：US5634001A

公开(公告)日：1997-05-27

申请号：US474441

申请日：1995-06-07

申请人： Steven W. Mittl ,  David E. Moran ,  Timothy J. O'Gorman ,  Kimball M. Watson

发明人： Steven W. Mittl ,  David E. Moran ,  Timothy J. O'Gorman ,  Kimball M. Watson

IPC分类号： G01R31/30 ,  G06F11/24 ,  G06F11/26 ,  G06F11/25

CPC分类号： G06F11/24 ,  G01R31/3004 ,  G06F11/261

摘要： A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times. A range of applied power supply voltages necessary to successfully perform a functional test of the microprocessor over a corresponding range of microprocessor cycle times is experimentally determined. Based on the calculated propagation delay degradation and on the range of applied power supply voltages, a guard band voltage differential for testing the microprocessor is determined.

摘要翻译： 提供了一种用于确定用于测试微处理器的保护带电压差的方法和系统。 保护带电压差近似微处理器在微处理器使用寿命期间预期发生的微​​处理器电路传播延迟劣化。 该系统和方法通过首先将微处理器划分成n个电路级模型的多个锥来执行。 创建定时仿真数据和劣化数据以分别表示每个电路级模型电路路径的定时操作，以及针对每个电路级模型的热电子对传播延迟劣化的影响。 在与微处理器的使用寿命和使用寿命相对应的时间，针对电路电平模型的每个电路路径，使用该数据来识别传播延迟。 传播延迟退化计算为这些时间的传播延迟之间的差异。 在微处理器循环时间的相应范围内成功执行微处理器的功能测试所需的一系列应用电源电压是实验确定的。 基于所计算的传播延迟劣化和所施加的电源电压的范围，确定用于测试微处理器的保护带电压差。