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1.发明授权Method to assess electromigration and hot electron reliability for microprocessors 失效评估微处理器的电迁移和热电子可靠性的方法
公开(公告)号：US5533197A
公开(公告)日：1996-07-02
申请号：US327151
申请日：1994-10-21
CPC分类号： G01R31/2858 , G01R31/2648 , G06F11/34 , G01R31/287
摘要： A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions. A timing equation is evaluated using distinctly identified components of the propagation delay degradation caused by electromigration and hot electron effects, to assess the toleration of the microprocessor to electromigration and hot electron induced propagation delay degradation.
摘要翻译： 提供了一种评估微机对由电迁移效应和热电子效应引起的传播时间劣化的容限的方法。 互连电阻（IR）劣化和漏极电流（DC）劣化的参考值在标称制造工艺和微处理器使用寿命应用条件下进行计算。 这些结果可以列出多个输出驱动器负载电容。 通过对实际测试条件分别缩放参考IR和DC降级值来计算测试IR降解和测试DC降解值。 在过程和终身环境条件下计算电迁移和电子电子效应引起的电路传播时间和传播延迟劣化。 使用由电迁移和热电子效应引起的传播延迟劣化的明确识别的分量来评估时序方程，以评估微处理器对电迁移和热电子诱导传播延迟退化的容忍度。
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2.发明授权Method to calculate hot-electron test voltage differential for assessing microprocessor reliability 失效计算热电子测试电压差的方法来评估微处理器的可靠性
公开(公告)号：US5634001A
公开(公告)日：1997-05-27
申请号：US474441
申请日：1995-06-07
CPC分类号： G06F11/24 , G01R31/3004 , G06F11/261
摘要： A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times. A range of applied power supply voltages necessary to successfully perform a functional test of the microprocessor over a corresponding range of microprocessor cycle times is experimentally determined. Based on the calculated propagation delay degradation and on the range of applied power supply voltages, a guard band voltage differential for testing the microprocessor is determined.
摘要翻译： 提供了一种用于确定用于测试微处理器的保护带电压差的方法和系统。 保护带电压差近似微处理器在微处理器使用寿命期间预期发生的微处理器电路传播延迟劣化。 该系统和方法通过首先将微处理器划分成n个电路级模型的多个锥来执行。 创建定时仿真数据和劣化数据以分别表示每个电路级模型电路路径的定时操作，以及针对每个电路级模型的热电子对传播延迟劣化的影响。 在与微处理器的使用寿命和使用寿命相对应的时间，针对电路电平模型的每个电路路径，使用该数据来识别传播延迟。 传播延迟退化计算为这些时间的传播延迟之间的差异。 在微处理器循环时间的相应范围内成功执行微处理器的功能测试所需的一系列应用电源电压是实验确定的。 基于所计算的传播延迟劣化和所施加的电源电压的范围，确定用于测试微处理器的保护带电压差。
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公开(公告)号：US08089160B2
公开(公告)日：2012-01-03
申请号：US11954866
申请日：2007-12-12
申请人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
发明人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect according to one embodiment includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to a top portion of the first via; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at a bottom end and to a metal power line at a top end thereof, wherein the first via is coupled to a first end of the buffer metal segment and the plurality of second vias are coupled to a second end of the buffer metal segment, such that the first via is horizontally off-set from all of the plurality of second vias, wherein the butter metal segment is substantially shorter in length than the metal power line.
摘要翻译： 根据一个实施例的IC互连包括位于电介质中并且在一端耦合到高电流器件的第一通孔; 位于电介质中并耦合到第一通孔的顶部的缓冲金属段; 以及多个第二通孔，其位于电介质中并在底端处连接到缓冲金属段，并在其顶端处连接到金属电源线，其中第一通孔耦合到缓冲金属段的第一端，并且 多个第二通孔耦合到缓冲金属段的第二端，使得第一通孔与所有多个第二通孔水平偏移，其中黄金金属段的长度短于金属电源线 。
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公开(公告)号：US20090152724A1
公开(公告)日：2009-06-18
申请号：US11954866
申请日：2007-12-12
申请人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
发明人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line.
摘要翻译： 公开了用于大电流器件的IC互连，其设计结构和方法。 IC互连的一个实施例包括位于电介质中的第一通孔，并在一端连接到高电流装置; 位于电介质中并在其另一端耦合到第一通孔的缓冲金属段; 以及多个第二通孔，其位于电介质中并且在一端处连接到缓冲金属段，并且在另一端处连接到金属电源线，其中所述缓冲金属段的长度短于金属电源线。
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公开(公告)号：US07384824B2
公开(公告)日：2008-06-10
申请号：US11362680
申请日：2006-02-27
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.
摘要翻译： 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的电介质层。 熔丝连接在电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。
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6.发明授权公开(公告)号：US08686478B2
公开(公告)日：2014-04-01
申请号：US13295392
申请日：2011-11-14
IPC分类号： H01L21/336
CPC分类号： H01L27/0635 , H01L21/8249 , H01L27/0802
摘要： Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.
摘要翻译： 通过在与电阻器相邻的俘获电荷区域中使用俘获电荷来改变电阻器和电阻器的电阻来对扩散电阻器进行电气编程的方法。 在一个实施例中，一种方法包括在衬底中形成扩散电阻器; 形成与扩散电阻相邻的俘获电荷区; 以及通过控制捕获的电荷区域中的捕获电荷来调节扩散电阻器的电阻。
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公开(公告)号：US20090253239A1
公开(公告)日：2009-10-08
申请号：US12062262
申请日：2008-04-03
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
IPC分类号： H01L21/331
CPC分类号： H01L29/41708 , H01L27/0629 , H01L27/0658 , H01L29/66272 , H01L29/7322 , H01L29/78
摘要： A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
摘要翻译： 一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。 可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。 该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。
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公开(公告)号：US20090140395A1
公开(公告)日：2009-06-04
申请号：US11949986
申请日：2007-12-04
申请人： Robert Edgar Davis , Robert Daniel Edwards , J. Edwin Hostetter, JR. , Ping-Chuan Wang , Kimball M. Watson
发明人： Robert Edgar Davis , Robert Daniel Edwards , J. Edwin Hostetter, JR. , Ping-Chuan Wang , Kimball M. Watson
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/76852 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/12 , H01L24/27 , H01L24/28 , H01L24/94 , H01L2221/68331 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/274 , H01L2924/0002 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2224/05552
摘要： One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.
摘要翻译： 在硅通孔（TSV）上形成一个或多个多层背面冶金（BSM）堆叠结构。 多层金属可以包括在半导体晶片背面上的铬的粘合层，铜的导电层，镍的扩散阻挡层和诸如金的诺贝尔金属层。 为了防止切割后铜的边缘侵蚀，形成镍层以密封铜边缘。 为了防止切割后镍层的边缘侵蚀，形成金层以密封铜层和镍层。
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公开(公告)号：US07064409B2
公开(公告)日：2006-06-20
申请号：US10605885
申请日：2003-11-04
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.
摘要翻译： 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝连接在第一电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。
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公开(公告)号：US07968975B2
公开(公告)日：2011-06-28
申请号：US12188234
申请日：2008-08-08
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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