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    Symmetrical Clock Distribution in Multi-Stage High Speed Data Conversion Circuits
    11.
    发明申请
    Symmetrical Clock Distribution in Multi-Stage High Speed Data Conversion Circuits 失效
    多级高速数据转换电路中的对称时钟分配

    公开(公告)号：US20080175277A1

    公开(公告)日：2008-07-24

    申请号：US12014094

    申请日：2008-01-15

    Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    IPC: H04J3/02

    CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

    Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

    Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

    Symmetrical clock distribution in multi-stage high speed data conversion circuits
    12.
    发明授权
    Symmetrical clock distribution in multi-stage high speed data conversion circuits 失效
    多级高速数据转换电路中的对称时钟分布

    公开(公告)号：US07319706B2

    公开(公告)日：2008-01-15

    申请号：US10609058

    申请日：2003-06-28

    Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    IPC: H04J3/02

    CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

    Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

    Abstract translation: 本发明提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

    System and method for testing the operation of a DLL-based interface
    14.
    发明授权
    System and method for testing the operation of a DLL-based interface 失效
    用于测试基于DLL的界面的操作的系统和方法

    公开(公告)号：US07289543B2

    公开(公告)日：2007-10-30

    申请号：US10778419

    申请日：2004-02-13

    Applicant: Guangming Yin ,  Bo Zhang

    Inventor： Guangming Yin ,  Bo Zhang

    IPC: H04J3/06

    CPC classification number: H04J3/04 ,  H04J3/0629 ,  H04L1/243 ,  H04L7/0008 ,  H04L25/14

    Abstract: A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

    Abstract translation: 高速比特流数据转换电路接收第一比特流并恢复来自第一比特流的时钟信号。 数据转换电路然后产生具有第二较低位速率的第二位流。 当第一比特流被分片以产生第二比特流时，控制环路将恢复的时钟信号的相位关系调整为第一比特流以最小化数据丢失。 在时钟电路内产生的参考时钟信号被分频以产生一个降低的频率参考时钟，该时钟信号与测试时钟信号多路复用以产生一个输出信号。 差分地分割输出信号产生用于内插器的一系列输入信号，其选择性地对控制环路所指示的输入信号进行加权和求和，以产生具有相对于第一位流的所需相位关系的恢复的时钟信号。

    Adaptable voltage control for a variable gain amplifier
    15.
    发明授权
    Adaptable voltage control for a variable gain amplifier 有权
    适用于可变增益放大器的电压控制

    公开(公告)号：US07262659B2

    公开(公告)日：2007-08-28

    申请号：US11559195

    申请日：2006-11-13

    Applicant: Mario Caresosa ,  Guangming Yin

    Inventor： Mario Caresosa ,  Guangming Yin

    IPC: H03F3/45

    CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

    Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

    Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
    17.
    发明授权
    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process 有权
    电流控制CMOS电路在低电压CMOS工艺中使用更高的电压源

    公开(公告)号：US06911855B2

    公开(公告)日：2005-06-28

    申请号：US10177031

    申请日：2002-06-21

    Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

    Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

    IPC: H03K3/356 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/094

    CPC classification number: H03K3/356043 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/09432

    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

    Abstract translation: 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C 3/4 MOS）逻辑。 包括逆变器/缓冲器，电平移位器，NAND，NOR，异或门，锁存器，触发器等的整个逻辑元件族都使用C 3 MOS技术实现。 通过将高速C“3”MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的三极管/ CMOS逻辑允许诸如光纤通信系统中使用的高速收发器之类的电路的更大集成。 C 3 O 3 MOS结构能够使用可能大于CMOS制造工艺所需的电压的电源电压，进一步提高电路的性能。

    Code independent charge transfer scheme for switched-capacitor digital-to-analog converter
    19.
    发明授权
    Code independent charge transfer scheme for switched-capacitor digital-to-analog converter 有权
    开关电容数模转换器的代码独立电荷转移方案

    公开(公告)号：US06437720B1

    公开(公告)日：2002-08-20

    申请号：US09785690

    申请日：2001-02-16

    Applicant: Guangming Yin ,  Bo Zhang

    Inventor： Guangming Yin ,  Bo Zhang

    IPC: H03M166

    CPC classification number: H03M1/0663 ,  H03M1/804

    Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

    Abstract translation: 公开了一种开关电容器数模转换器电路。 开关电容器数模转换器电路包括用于每个电容器分支的交叉开关，交叉开关用于消除共享相同参考电压的数模转换器模块之间的交叉干扰。

    MULTI-CASCODE AMPLIFIER BIAS TECHNIQUES
    20.
    发明申请
    MULTI-CASCODE AMPLIFIER BIAS TECHNIQUES 有权
    多芯片放大器偏置技术

    公开(公告)号：US20140043102A1

    公开(公告)日：2014-02-13

    申请号：US13570062

    申请日：2012-08-08

    Applicant: Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

    Inventor： Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

    IPC: H03F1/22 ,  H03F3/68

    CPC classification number: H03F1/223 ,  H03F3/193

    Abstract: Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

    Abstract translation: 用于产生多共源共栅放大器偏置电压的技术。 在一方面，提供了一种多共源共栅偏压网络，偏置网络中的每个晶体管是多共源共栅放大器中对应的晶体管的复制品，使多级共源共栅放大器中的晶体管能够精确偏置。 在另一方面，用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开提供，以有利地将放大器电压源与偏置网络电压源的变化分离。 在另一方面，多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压，所以可以以这种方式调节放大器的增益，而不将可变增益元件直接引入放大器信号路径。

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