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30 条记录 (耗时 0.033 秒)

    Voltage controlled oscillator including a plurality of differential amplifiers
    12.
    发明授权
    Voltage controlled oscillator including a plurality of differential amplifiers 有权
    压控振荡器包括多个差分放大器

    公开(公告)号：US06252467B1

    公开(公告)日：2001-06-26

    申请号：US09360695

    申请日：1999-07-26

    申请人： Tsutomu Yoshimura

    发明人： Tsutomu Yoshimura

    IPC分类号： H03B524

    CPC分类号： H03K3/0322

    摘要： A differential VCO includes a ring oscillator with a plurality of differential buffers connected in a ring, a bias circuit including a replica circuit of the differential buffers, and a differential gain increasing circuit for increasing differential gain of the differential buffers. Even when the differential gain of the differential buffer lowers as a result of obtaining a clock signal of higher frequency, the ring oscillator oscillates smooth.

    摘要翻译： 差分VCO包括具有连接在环中的多个差分缓冲器的环形振荡器，包括差分缓冲器的复制电路的偏置电路和用于增加差分缓冲器的微分增益的差分增益增加电路。 即使由于获得较高频率的时钟信号而导致差分缓冲器的差分增益降低，​​所以环形振荡器振荡平稳。

    Digital synchronous circuit for stably generating output clock synchronized with input data
    14.
    发明授权
    Digital synchronous circuit for stably generating output clock synchronized with input data 失效
    数字同步电路，用于稳定地产生与输入数据同步的输出时钟

    公开(公告)号：US06987825B1

    公开(公告)日：2006-01-17

    申请号：US09584728

    申请日：2000-06-01

    申请人： Tsutomu Yoshimura ,  Harufusa Kondoh

    发明人： Tsutomu Yoshimura ,  Harufusa Kondoh

    IPC分类号： H04L7/00

    CPC分类号： H03K5/135 ,  H03K2005/00156 ,  H04L7/0338

    摘要： The present digital synchronous circuit includes a clock generating circuit for outputting a plurality of clock signals CLK1 to CLKn, a plurality of first latch circuits, each for receiving an input data signal DIN at a data input terminal and for receiving a corresponding clock signal at a clock input terminal, a plurality of second latch circuits, each for latching, in response to the receipt of a control signal LC, an output signal from a corresponding first latch circuit, and a control circuit for receiving input data signal DIN to generate control signal LC. Control circuit outputs control signal LC after a delay of a prescribed period of time after the change in input data signal DIN. As a result, the adverse influence of the meta-stable state that occurs when sampling an asynchronous input data signal DIN is avoided, while at the same time, the chip size and power consumption are limited.

    摘要翻译： 本数字同步电路包括用于输出多个时钟信号CLK 1至CLK n的时钟产生电路，多个第一锁存电路，每个用于在数据输入端接收输入数据信号DIN，并用于接收相应的时钟信号 时钟输入端子，多个第二锁存电路，每个用于响应于控制信号LC的接收而锁存来自对应的第一锁存电路的输出信号，以及用于接收输入数据信号DIN以产生控制的控制电路 信号LC。 控制电路在输入数据信号DIN改变后的规定时间内延迟输出控制信号LC。 结果，避免了在对异步输入数据信号DIN采样时发生的元稳定状态的不利影响，同时芯片尺寸和功耗受到限制。

    Rubber vulcanizate, process for its production, and polymer composition, rubber composition and vulcanizable rubber composition used in the process
    15.
    发明申请
    Rubber vulcanizate, process for its production, and polymer composition, rubber composition and vulcanizable rubber composition used in the process 审中-公开
    橡胶硫化橡胶，其生产方法和聚合物组合物，橡胶组合物和可硫化橡胶组合物用于该方法

    公开(公告)号：US20050070667A1

    公开(公告)日：2005-03-31

    申请号：US10496804

    申请日：2002-11-27

    申请人： Takashi Toya ,  Shinji Komiyama ,  Tsutomu Yoshimura

    发明人： Takashi Toya ,  Shinji Komiyama ,  Tsutomu Yoshimura

    IPC分类号： C08L9/02 ,  C08L33/00 ,  C08L33/12 ,  C08F8/00

    CPC分类号： C08L9/02 ,  C08L33/00 ,  C08L33/12 ,  C08L2666/04 ,  C08L2666/08

    摘要： This invention provides a rubber vulcanizate of a nitrile group-containing copolymer rubber, exhibiting enhanced ozone resistance. The rubber vulcanizate is made by heat-treating a polymer composition comprising 40-90 wt. % of a nitrile group-containing copolymer rubber (1), and 60-10 wt. % of particles having an average particle diameter of not larger than 10 μm comprised of an acrylic resin (2) comprising methyl acrylate or methacrylate units as the main structural units and containing not larger than 0.01 eq. wt., per 100 g of acrylic resin (2), of a crosslink-forming functional group, at a temperature in the range of (T+20)° C. to (T+90)° C. wherein T is a temperature which is selected from glass transition temperature of acrylic resin (2) and melting temperature of acrylic resin (2), and is higher than the other of the two temperatures, to thereby prepare a rubber composition; incorporating a vulcanizer in the rubber composition; and vulcanizing the thus-obtained vulcanizable rubber composition.

    摘要翻译： 本发明提供了含有腈基的共聚物橡胶的橡胶硫化橡胶，具有增强的耐臭氧性。 橡胶硫化橡胶通过热处理包含40-90wt。 含腈基共聚物橡胶（1）的％，和60〜10重量％ 平均粒径不大于10μm的由包含丙烯酸甲酯或甲基丙烯酸甲酯单元作为主要结构单元并且不大于0.01当量的丙烯酸树脂（2）组成的颗粒的百分比。 在（T + 20）℃至（T + 90）℃范围内的温度下，每100g丙烯酸树脂（2）交联形成官能团的重量百分数。其中T是温度 其选自丙烯酸树脂（2）的玻璃化转变温度和丙烯酸树脂（2）的熔融温度，并且高于两个温度中的另一个，从而制备橡胶组合物; 在橡胶组合物中加入硫化剂; 并硫化由此获得的可硫化橡胶组合物。

    Digital data transmission system
    16.
    发明授权
    Digital data transmission system 失效
    数字数据传输系统

    公开(公告)号：US06396888B1

    公开(公告)日：2002-05-28

    申请号：US09032944

    申请日：1998-03-02

    申请人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    发明人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    IPC分类号： H04L706

    CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/0891 ,  H04J3/0614 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/04

    摘要： A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

    摘要翻译： 提供了一种用于使用所需的最小数量的信号线和简单的电路结构来发送数字数据，帧脉冲信号和时钟的数字数据传输系统。 接收与时钟（CK）复用的帧脉冲信号（FP）的多时钟（CKFP）的信号分离电路（46）包括：时钟恢复电路（47），用于通过与时钟（CK）同步再现再生时钟（RCK） 使用同步环路的多个时钟（CKFP）和基于恢复时钟（RCK）从多个时钟（CKFP）分离恢复的帧脉冲信号（RFP）的帧脉冲信号分离电路（48）。

    Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit
    17.
    发明授权
    Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit 失效
    半导体器件可以通过停止时钟信号的供应来减少待机电流，并且可以保持内部电路的状态

    公开(公告)号：US06278303B1

    公开(公告)日：2001-08-21

    申请号：US09437739

    申请日：1999-11-10

    申请人： Jingo Nakanishi ,  Hiroshi Makino ,  Tsutomu Yoshimura

    发明人： Jingo Nakanishi ,  Hiroshi Makino ,  Tsutomu Yoshimura

    IPC分类号： H03L706

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  H03L7/0802 ,  H03L7/0891 ,  H03L7/0995 ,  Y02D10/128 ,  Y02D50/20

    摘要： A clock circuit is provided including a clock supply circuit that can cease clock supply according to a control signal, a PLL circuit maintaining clock synchronization, and a dummy circuit. Synchronization of the internal clock signal is maintained by the PLL circuit and the dummy circuit even in a standby state. In returning to an active state from a standby state, an unstable clock signal arising from unstable locking of the PLL circuit will not be applied to the internal circuit. Therefore, the information in the latch circuit in the internal circuit can be maintained.

    摘要翻译： 提供了一种时钟电路，包括可以根据控制信号停止时钟供给的时钟供应电路，保持时钟同步的PLL电路和虚拟电路。 即使处于待机状态，PLL电路和虚拟电路仍保持内部时钟信号的同步。 在从待机状态返回到活动状态时，由PLL电路不稳定锁定引起的不稳定的时钟信号不会被施加到内部电路。 因此，可以保持内部电路中的锁存电路中的信息。

    Automatic frequency correction PLL circuit
    20.
    发明授权
    Automatic frequency correction PLL circuit 有权
    自动频率校正PLL电路

    公开(公告)号：US07519140B2

    公开(公告)日：2009-04-14

    申请号：US11087591

    申请日：2005-03-24

    申请人： Tsutomu Yoshimura

    发明人： Tsutomu Yoshimura

    IPC分类号： H03M1/12

    CPC分类号： H03L7/10 ,  H03L7/099

    摘要： An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

    摘要翻译： 自动频率校正锁相环（PLL）电路包括模拟控制电路和数字控制电路。 数字控制电路包括接收模拟控制电压的高侧比较器和低侧比较器，状态监视电路以及计数器和解码器电路。 高侧比较器和低侧比较器中的至少一个包括阈值切换电路，其选择性地提供第一阈值电压和第二阈值电压，第一和第二阈值电压具有不同的幅度。 当模拟控制电压在高侧阈值电压和低侧阈值电压之间保持稳定时，阈值开关电路提供第一阈值电压时，状态监视电路将阈值切换电路从第一阈值电压切换到第二阈值电压 阈值电压，从而扩大高侧阈值电压与低侧阈值电压之间的间隔。