公开(公告)号：US20070148942A1

公开(公告)日：2007-06-28

申请号：US11479242

申请日：2006-06-29

申请人： Sang-Oh Lee ,  Sung-Kwon Lee

发明人： Sang-Oh Lee ,  Sung-Kwon Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76804 ,  H01L27/10888

摘要： A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

摘要翻译： 用于形成半导体器件的接触孔的方法包括：在衬底上形成下部图案; 在下图案上形成旋涂玻璃（SOG）层; 在SOG层上进行第一固化过程; 形成露出SOG层的一部分的开口; 在对应于开口的下部的SOG层上进行第二固化过程; 以及形成暴露下部图案的接触孔。

公开(公告)号：US07557039B2

公开(公告)日：2009-07-07

申请号：US11479242

申请日：2006-06-29

申请人： Sang-Oh Lee ,  Sung-Kwon Lee

发明人： Sang-Oh Lee ,  Sung-Kwon Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76804 ,  H01L27/10888

摘要： A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

摘要翻译： 用于形成半导体器件的接触孔的方法包括：在衬底上形成下部图案; 在下图案上形成旋涂玻璃（SOG）层; 在SOG层上进行第一固化过程; 形成露出SOG层的一部分的开口; 在对应于开口的下部的SOG层上进行第二固化过程; 以及形成暴露下部图案的接触孔。

公开(公告)号：US07589026B2

公开(公告)日：2009-09-15

申请号：US11743669

申请日：2007-05-03

申请人： Sung-Kwon Lee ,  Jae-Young Lee

发明人： Sung-Kwon Lee ,  Jae-Young Lee

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/31138

摘要： A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.

摘要翻译： 在半导体器件中制造精细图案的方法包括在蚀刻目标层上形成第一聚合物层和第二聚合物层。 第二聚合物层在第一衬底温度下被图案化。 使用不包括氧（O 2）的蚀刻气体在第二衬底温度下蚀刻第一聚合物层。 使用图案化的第二聚合物层作为蚀刻掩模蚀刻第一聚合物层。 然后使用蚀刻的第一聚合物层和蚀刻的第二聚合物层作为蚀刻掩模蚀刻蚀刻目标层。

公开(公告)号：US07534553B2

公开(公告)日：2009-05-19

申请号：US11264427

申请日：2005-10-31

申请人： Sung-Kwon Lee ,  Gyu-Dong Park

发明人： Sung-Kwon Lee ,  Gyu-Dong Park

IPC分类号： G03F7/26

CPC分类号： H01L21/02118 ,  G03F7/09 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/312

摘要： A method for fabricating a semiconductor device is provided. The method includes: preparing a substrate defined as active regions and inactive regions and provided with a plurality of conductive patterns; forming a buffer layer over the plurality of conductive patterns; forming an organic material having fluidity better than that of a photoresist layer on the buffer layer; flowing the organic material between the conductive patterns through a thermal treatment process, thereby filling a portion of each gap between the conductive patterns; forming the photoresist layer over the organic material and the buffer layer; forming a plurality of photoresist patterns opening the active regions through a photo-exposure process and a developing process; and performing an ion-implantation process using the plurality of photoresist patterns, thereby forming a plurality of junction regions in the active regions of the substrate.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：制备定义为有源区和非活性区的衬底，并设置有多个导电图案; 在所述多个导电图案上形成缓冲层; 形成流动性优于缓冲层上的光致抗蚀剂层的有机材料; 通过热处理工艺使有机材料在导电图案之间流动，由此填充导电图案之间的每个间隙的一部分; 在有机材料和缓冲层上形成光致抗蚀剂层; 形成通过曝光过程和显影过程打开活性区域的多个光致抗蚀剂图案; 以及使用所述多个光致抗蚀剂图案进行离子注入工艺，从而在所述衬底的有源区域中形成多个结区域。

公开(公告)号：US07405091B2

公开(公告)日：2008-07-29

申请号：US11020599

申请日：2004-12-21

申请人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

摘要翻译： 本发明是一种用于测试接触开口的方法，其能够有效地测试在线的接触开口缺陷以确保批量生产率。 该方法包括以下步骤：执行用于形成接触的光刻工艺; 在对至少一个晶片取样之后进行接触蚀刻工艺形成接触孔; 在设置有接触孔的晶片上沉积导电层; 隔离接触孔内的导电层; 执行用于测试接触开放界面的测试以检查导电层和导电层的下部结构之间的界面中是否存在剩余层; 并且基于测试结果执行蚀刻主批次的接触的处理。

公开(公告)号：US07365000B2

公开(公告)日：2008-04-29

申请号：US10876783

申请日：2004-06-28

申请人： Sung-Kwon Lee ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Min-Suk Lee

IPC分类号： H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/02063 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31116 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823475

摘要： Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件能够防止层间绝缘层在湿式清洁过程中由于依赖于经历固化过程的SOG层的厚度和克服缺陷而产生的密度差而被损坏 这是由于某个区域的接触开口不正确以及由APL层的微小空隙发生的冲击造成的。 特别地，该方法包括以下步骤：在衬底上形成多个导电结构; 形成旋涂玻璃层; 固化旋涂玻璃层; 在旋涂玻璃层上形成先进的平面化层; 以及通过选择性地蚀刻高级平坦化层和旋涂玻璃层而形成多个接触孔，从而暴露基板的部分。

公开(公告)号：US20080081446A1

公开(公告)日：2008-04-03

申请号：US11904401

申请日：2007-09-27

申请人： Sung-Kwon Lee ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Min-Suk Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

摘要： A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成第一图案，在第一图案上形成氧化物基层，在氧化物基层上形成硬掩模层，在第一衬底温度下蚀刻硬掩模层， 并且蚀刻所述氧化物基层以形成第二图案，其中所述氧化物基层在使用包含氟（F）和碳（C））为主要气体的第二基板温度下蚀刻，所述第二基板温度大于所述第一基板温度 蚀刻气体。

公开(公告)号：US07314792B2

公开(公告)日：2008-01-01

申请号：US11321591

申请日：2005-12-30

申请人： Myung-Ok Kim ,  Tae-Woo Jung ,  Sung-Kwon Lee ,  Sea-Ug Jang

发明人： Myung-Ok Kim ,  Tae-Woo Jung ,  Sung-Kwon Lee ,  Sea-Ug Jang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/331 ,  H01L21/76

CPC分类号： H01L21/31116 ,  H01L29/66621

摘要： A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

摘要翻译： 提供一种制造半导体器件的晶体管的方法。 该方法包括：在包括底部结构的衬底中形成器件隔离层，从而限定有源区; 将活性区域蚀刻到预定深度以形成多个凹部结构，每个凹部结构具有平坦的底部，其临界尺寸（CD）大于顶部部分的临界尺寸; 并且在所述凹部结构上依次形成栅极氧化物层和金属层; 以及图案化栅极氧化物层和金属层以形成多个栅极结构。

公开(公告)号：US07199013B2

公开(公告)日：2007-04-03

申请号：US11262222

申请日：2005-10-28

申请人： Sung-Kwon Lee

发明人： Sung-Kwon Lee

IPC分类号： H01L21/8247

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.

公开(公告)号：US07122467B2

公开(公告)日：2006-10-17

申请号：US10879733

申请日：2004-06-30

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/97

摘要： Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有通过在湿式清洗过程中防止对层间绝缘层的损坏而获得的改进的工艺余量。 特别地，该方法包括以下步骤：形成具有第一导电层和第一硬掩模的堆叠图案的多个第一导电图案; 形成第一导电层上第一导电材料与第一硬掩模之间的高度的良好间隙填充性能的第一层间绝缘层; 形成第二层间绝缘层; 形成第二导电层，所述第二导电层与所述多个所述第一导电图案之间的所述第一导电层接触通过所述第一和第二层间绝缘层; 形成第三层间绝缘层; 形成多个第二导电图案; 形成第四层间绝缘层; 以及形成与所述第二导电层接触的第三导电层。