公开(公告)号：US06455364B1

公开(公告)日：2002-09-24

申请号：US09526686

申请日：2000-03-15

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L218249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US06713790B2

公开(公告)日：2004-03-30

申请号：US10212799

申请日：2002-08-07

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US06858454B1

公开(公告)日：2005-02-22

申请号：US10674523

申请日：2003-10-01

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

IPC分类号： G01N21/21 ,  G01N21/35 ,  H01L21/66

CPC分类号： G01N21/3563 ,  G01N21/211

摘要： A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.

摘要翻译： 一种测量半导体构成元件含量的方法采用以下步骤：通过使用分光椭圆偏光度法评估在半导体衬底上形成的SiGeC层的膜厚度; 测量SiGeC层的红外吸收光谱; 并根据SiGeC层的膜厚和红外吸收光谱获得SiGeC层的C含量。 该方法：通过使用分光椭偏仪评估获得SiGeC层的表观Ge含量; 并且基于表观Ge含量和C含量获得SiGeC层的实际Ge含量。 根据上述方法可以容易且精确地测量SiGeC层的构成元素含量。

公开(公告)号：US06987072B2

公开(公告)日：2006-01-17

申请号：US11009020

申请日：2004-12-13

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： H01L21/31

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06720587B2

公开(公告)日：2004-04-13

申请号：US10048562

申请日：2002-02-04

申请人： Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo ,  Yoshihiko Kanzawa

发明人： Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo ,  Yoshihiko Kanzawa

IPC分类号： H01L31109

CPC分类号： H01L22/20 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An initial estimated value of a process condition is set, and a structure of an element of a semiconductor device is estimated by a process simulator, after which an estimated value of a physical amount measurement value is calculated. Then, an actual measurement value of a physical amount of the element of the semiconductor device, which is obtained by an optical evaluation method, and a theoretical calculated value thereof are compared with each other, so as to obtain a probable structure of the measured semiconductor device element by using, for example, a simulated annealing, or the like. A process condition in a process for other semiconductor device elements can be corrected by using the results.

摘要翻译： 设置处理条件的初始估计值，并且通过处理模拟器估计半导体器件的元件的结构，之后计算物理量测量值的估计值。 然后，将通过光学评估方法获得的半导体器件的元件的物理量的实际测量值和理论计算值彼此进行比较，以获得测量的半导体的可能结构 器件元件，例如使用模拟退火等。 可以通过使用结果来校正其他半导体器件元件的处理过程。

公开(公告)号：US06649496B2

公开(公告)日：2003-11-18

申请号：US09979258

申请日：2001-11-21

申请人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

发明人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

IPC分类号： H01L2120

CPC分类号： C23C16/22 ,  C30B25/02 ,  C30B29/52

摘要： After the surface of a Si substrate (1) has been pretreated, an SiGeC layer (2) is formed on the Si substrate (1) using an ultrahigh vacuum chemical vapor deposition (UHV-CVD) apparatus. During this process step, the growth temperature of the SiGeC layer (2) is set at 490° C. or less and Si2H6, GeH4 and SiH3CH3 are used as Si, Ge and C sources, respectively, whereby the SiGeC layer (2) with good crystallinity can be formed.

摘要翻译： 在Si衬底（1）的表面经过预处理之后，使用超高真空化学气相沉积（UHV-CVD）装置在Si衬底（1）上形成SiGeC层（2）。 在该工艺步骤中，SiGeC层（2）的生长温度设定为490℃以下，Si 2 H 6，GeH 4，SiH 3 CH 3分别用作Si，Ge，C源，SiGeC层（2）与 可以形成良好的结晶度。

公开(公告)号：US06645836B2

公开(公告)日：2003-11-11

申请号：US09979305

申请日：2001-11-21

申请人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

发明人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

IPC分类号： H01L2130

CPC分类号： H01L29/1608 ,  C30B29/06 ,  C30B29/52 ,  C30B33/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02667 ,  H01L29/1054 ,  H01L29/165

摘要： A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

摘要翻译： 对其上沉积有SiGeC晶体层8的Si衬底1进行退火，以在Si衬底1上形成退火的SiGeC晶体层10.退火的SiGeC晶体层包括晶格释放且几乎不具有位错的SiGeC晶体层7 ，以及分散在基体SiGeC晶体层7中的Sic微晶6.然后在退火的SiGeC晶体层10上沉积Si晶体层，形成几乎不具有位错的应变Si晶体层4。

公开(公告)号：US06838395B1

公开(公告)日：2005-01-04

申请号：US10330080

申请日：2002-12-30

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： C30B1/00 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06660393B2

公开(公告)日：2003-12-09

申请号：US10383743

申请日：2003-03-10

申请人： Tohru Saitoh ,  Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Minoru Kubo

发明人： Tohru Saitoh ,  Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Minoru Kubo

IPC分类号： C30B2934

CPC分类号： H01L29/161 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  Y10T428/12674 ,  Y10T428/265

摘要： A B-doped Si1−x−yGexCy layer 102 (where 0

摘要翻译： 使用UHV-CVD工艺在Si衬底101上外延生长B掺杂的Si1-x-yGexCy层102（其中0

公开(公告)号：US20060225642A1

公开(公告)日：2006-10-12

申请号：US10402239

申请日：2003-03-31

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Akira Asai ,  Teruhito Ohnishi

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Akira Asai ,  Teruhito Ohnishi

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B25/04 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661 ,  H01L29/1054

摘要： A method of forming semiconductor crystal of the present invention comprises the steps of heating a Si substrate to clean a surface of the Si substrate, epitaxially growing Si crystal on the Si substrate inside a crystal growth chamber at a growth temperature lower than a substrate temperature of the Si substrate in the cleaning step and higher than a growth temperature at which SiGe crystal is epitaxially grown later, and epitaxially growing the SiGe crystal on the Si crystal.

摘要翻译： 本发明的半导体晶体的形成方法包括以下步骤：加热Si衬底以清洁Si衬底的表面，在晶体生长室内的Si衬底上外延生长Si晶体，生长温度低于衬底温度 Si衬底在高于SiGe晶体后来生长的生长温度以及在Si晶体上外延生长SiGe晶体。