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公开(公告)号：US20230089702A1
公开(公告)日：2023-03-23
申请号：US17685981
申请日：2022-03-03
Applicant: KIOXIA CORPORATION
Inventor： Hironori UCHIKAWA
Abstract: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.
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公开(公告)号：US20220261312A1
公开(公告)日：2022-08-18
申请号：US17412026
申请日：2021-08-25
Applicant: Kioxia Corporation
Inventor： Takahiro KUBOTA , Daiki WATANABE , Hironori UCHIKAWA
IPC: G06F11/10
Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller. The memory controller is configured to calculate an ath soft-input value for an ath component code based on correction information of the ath component code (1≤a≤ni) of an ith dimension (1≤i≤N), ath reliability information, and a syndrome value of the ath component code, to calculate a decoded word of the ath component code, the ath correction information, and the ath reliability information by inputting the ath soft-input value and executing a decoding process of the ath component code, to store the ath correction information and bth correction information indicating a corrected position of a bth component code (1≤b≤nj) of a jth dimension (j≠i, 1≤j≤N) in a correction information memory, to store the ath reliability information in a reliability information memory, and to output an output decoded word calculated from the read information and the reliability information of each component code.
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公开(公告)号：US20210264990A1
公开(公告)日：2021-08-26
申请号：US17244246
申请日：2021-04-29
Applicant: Kioxia Corporation
Inventor： Noboru SHIBATA , Hironori UCHIKAWA , Taira SHIBUYA
Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
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公开(公告)号：US20240185930A1
公开(公告)日：2024-06-06
申请号：US18527941
申请日：2023-12-04
Applicant: Kioxia Corporation
Inventor： Noboru SHIBATA , Hironori UCHIKAWA
CPC classification number: G11C16/26 , G11C7/08 , G11C8/14 , G11C16/0483 , G11C16/08 , G11C16/10 , H10B43/27 , H10B43/35 , G11C2207/2245
Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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公开(公告)号：US20230297273A1
公开(公告)日：2023-09-21
申请号：US17887873
申请日：2022-08-15
Applicant: Kioxia Corporation
Inventor： Takahiro KUBOTA , Hironori UCHIKAWA , Yuta KUMANO
IPC: G06F3/06
CPC classification number: G06F3/0658 , G06F3/0619 , G06F3/0679
Abstract: A memory controller determines the number of pieces of correction information of an a-th correction information for each of M component codes according to a value based on the number of component codes, and determines a correction information address which is an address on a correction information memory of the a-th correction information based on the number of pieces of correction information. The memory controller calculates an a-th soft-input value for an a-th component code, inputting the a-th soft-input value to execute decoding processing of the a-th component code, calculates a decoded word of the a-th component code, a-th correction information, and a-th reliability information, stores the a-th correction information and b-th correction information indicating a b-th corrected location (1≤b≤nj) in a j-th dimension (j≠i, 1≤j≤N) in the correction information address of the correction information memory, stores a-th reliability information in a reliability information memory, and outputs an output decoded word calculated from the read information and the reliability information of each component code.
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Patent Agency Ranking
公开(公告)号：US20220262443A1
公开(公告)日：2022-08-18
申请号：US17735196
申请日：2022-05-03
Applicant: KIOXIA CORPORATION
Inventor： Noboru SHIBATA , Hironori UCHIKAWA
IPC: G11C16/26 , H01L27/11582 , H01L27/1157 , G11C16/04 , G11C8/14 , G11C16/08 , G11C16/10 , G11C7/08
Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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公开(公告)号：US20210091792A1
公开(公告)日：2021-03-25
申请号：US16806322
申请日：2020-03-02
Applicant: KIOXIA CORPORATION
Inventor： Naoko KIFUNE , Hironori UCHIKAWA
Abstract: A memory system includes a nonvolatile memory and a memory controller that encodes first XOR data generated by performing an exclusive OR operation on pieces of user data, wherein a value of each bit of the XOR data is generated by performing an exclusive OR operation on values of bits that are at one of a plurality of bit positions of a piece of user data, generates codewords by encoding the plurality of pieces of user data and the generated XOR data, respectively, and stores the codewords in the nonvolatile memory. The memory controller also performs a read operation by reading the codewords from the nonvolatile memory and decoding them. When the decoding of two or more of the codewords fails, the memory controller generates second XOR data, and corrects the value of one of the bits corresponding to a codeword whose decoding failed, based on the second XOR data.
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公开(公告)号：US20240372567A1
公开(公告)日：2024-11-07
申请号：US18771866
申请日：2024-07-12
Applicant: KIOXIA CORPORATION
Inventor： Shinichi KANNO , Hironori UCHIKAWA
Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
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公开(公告)号：US20240264749A1
公开(公告)日：2024-08-08
申请号：US18432257
申请日：2024-02-05
Applicant: Kioxia Corporation
Inventor： Takahiro KUBOTA , Hironori UCHIKAWA
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: A memory system includes a non-volatile memory configured to store an error correction codes and a memory controller. The memory controller is configured to obtain read information from the non-volatile memory, perform a first decoding process on the read information to output a plurality of decoding results respectively corresponding to a plurality of elements provided in the read information, perform a cancellation process for returning the decoding results satisfying a condition among the plurality of decoding results to values prior to decoding in response to the first decoding process being not successful, and perform a second decoding process using the plurality of decoding results after performing the cancelation process.
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公开(公告)号：US20240086280A1
公开(公告)日：2024-03-14
申请号：US18168388
申请日：2023-02-13
Applicant: Kioxia Corporation
Inventor： Takahiro KUBOTA , Hironori UCHIKAWA
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/3466
Abstract: A memory system includes a non-volatile memory and a memory controller that encodes data with an error correction code and stores the encoded data in the non-volatile memory. The memory controller executes first processing which is at least a part of first decoding processing using read information read from the non-volatile memory, uses statistical information of a processing result of the first processing to estimate a first indicator indicating a ratio of hard errors among bit errors in the read information, determines parameters for second decoding processing having a higher latency than the first processing according to the first indicator, and executes the second decoding processing by using the determined parameters and the read information.
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