公开(公告)号：US20230282276A1

公开(公告)日：2023-09-07

申请号：US18196263

申请日：2023-05-11

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Tokumasa HARA

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G06F13/16 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459 ,  G06F13/16 ,  G11C16/0483 ,  G11C2211/5648

Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

公开(公告)号：US20230238059A1

公开(公告)日：2023-07-27

申请号：US18295504

申请日：2023-04-04

Applicant: KIOXIA CORPORATION

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G06F11/10 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/14 ,  G06F3/0679 ,  G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G11C16/10

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US20220157387A1

公开(公告)日：2022-05-19

申请号：US17471810

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page

公开(公告)号：US20220148651A1

公开(公告)日：2022-05-12

申请号：US17582330

申请日：2022-01-24

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/06

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US20220076772A1

公开(公告)日：2022-03-10

申请号：US17178554

申请日：2021-02-18

Applicant: Kioxia Corporation

Inventor： Itaru HIDA ,  Tokumasa HARA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/50

Abstract: According to one embodiment, a memory system includes a non-volatile memory provided with a plurality of memory cells, and a memory controller. The memory controller reads data subjected to error-mitigation encoding from the non-volatile memory, the data including determination information indicating whether or not a value is changed by the error-mitigation encoding, executes error-mitigation decoding on the read data, re-executes the error-mitigation encoding on a decoding result obtained by the error-mitigation decoding, and compares the determination information included in the read data with determination information included in data obtained by re-executing the error-mitigation encoding and outputs a comparison result.

公开(公告)号：US20210158867A1

公开(公告)日：2021-05-27

申请号：US17016765

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G06F11/10 ,  G06F3/06

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US20210082497A1

公开(公告)日：2021-03-18

申请号：US17014293

申请日：2020-09-08

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/06

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.