公开(公告)号：US20240363166A1

公开(公告)日：2024-10-31

申请号：US18766000

申请日：2024-07-08

Applicant: Kioxia Corporation

Inventor： Hiroshi SUKEGAWA ,  Ikuo MAGAKI ,  Tokumasa HARA ,  Shirou FUJITA

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H10B43/27

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  H10B43/27

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

公开(公告)号：US20220206892A1

公开(公告)日：2022-06-30

申请号：US17367189

申请日：2021-07-02

Applicant: Kioxia Corporation

Inventor： Yasuyuki IMAIZUMI ,  Tokumasa HARA ,  Toshiyuki YAMAGISHI

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/29

Abstract: A memory system includes a non-volatile memory including at least one memory cell, a buffer, and a memory controller. The memory controller acquires first data from the buffer. The first data includes a plurality of bits of data. The memory controller generates second data by performing a randomization process on the first data, generates a flag that is information used to identify an error suppression encoding process, based on the second data, and stores the flag in the buffer. The memory controller acquires third data and the flag from the buffer. The third data is 1-bit data of the first data. The memory controller generates storage data by performing the error suppression encoding process based on the acquired flag and the randomization process on the third data, and writes the storage data into the memory cell.

公开(公告)号：US20250069654A1

公开(公告)日：2025-02-27

申请号：US18948133

申请日：2024-11-14

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US20220101915A1

公开(公告)日：2022-03-31

申请号：US17545470

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G06F11/10 ,  G11C16/10

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US20230410899A1

公开(公告)日：2023-12-21

申请号：US18364524

申请日：2023-08-03

Applicant: KIOXIA CORPORATION

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/0679

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US20230350571A1

公开(公告)日：2023-11-02

申请号：US18348061

申请日：2023-07-06

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Tokumasa HARA

IPC: G06F12/0875 ,  G06F3/06 ,  G06F13/16 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0875 ,  G06F13/16 ,  G11C7/1063 ,  G11C16/10 ,  G11C16/26 ,  G11C7/24

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

公开(公告)号：US20230223083A1

公开(公告)日：2023-07-13

申请号：US18121344

申请日：2023-03-14

Applicant: Kioxia Corporation

Inventor： Hiroshi SUKEGAWA ,  Ikuo MAGAKI ,  Tokumasa HARA ,  Shirou FUJITA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H10B43/27 ,  G06F3/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  H10B43/27 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

公开(公告)号：US20240339160A1

公开(公告)日：2024-10-10

申请号：US18746964

申请日：2024-06-18

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/102 ,  G11C16/30 ,  G11C16/3404

Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.

公开(公告)号：US20240005988A1

公开(公告)日：2024-01-04

申请号：US18467271

申请日：2023-09-14

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US20220075521A1

公开(公告)日：2022-03-10

申请号：US17527851

申请日：2021-11-16

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Tokumasa HARA

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/0875 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.