Abstract:
A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.
Abstract:
A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.
Abstract:
Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.
Abstract:
A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.
Abstract:
Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.
Abstract:
Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.
Abstract:
A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.
Abstract:
Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.
Abstract:
A high sensitivity image sensor comprises an epitaxial layer of silicon that is intrinsic or lightly p doped (such as a doping level less than about 1013 cm−3). CMOS or CCD circuits are fabricated on the front-side of the epitaxial layer. Epitaxial p and n type layers are grown on the backside of the epitaxial layer. A pure boron layer is deposited on the n-type epitaxial layer. Some boron is driven a few nm into the n-type epitaxial layer from the backside during the boron deposition process. An anti-reflection coating may be applied to the pure boron layer. During operation of the sensor a negative bias voltage of several tens to a few hundred volts is applied to the boron layer to accelerate photo-electrons away from the backside surface and create additional electrons by an avalanche effect. Grounded p-wells protect active circuits as needed from the reversed biased epitaxial layer.
Abstract:
A high sensitivity image sensor comprises an epitaxial layer of silicon that is intrinsic or lightly p doped (such as a doping level less than about 1013 cm−3). CMOS or CCD circuits are fabricated on the front-side of the epitaxial layer. Epitaxial p and n type layers are grown on the backside of the epitaxial layer. A pure boron layer is deposited on the n-type epitaxial layer. Some boron is driven a few nm into the n-type epitaxial layer from the backside during the boron deposition process. An anti-reflection coating may be applied to the pure boron layer. During operation of the sensor a negative bias voltage of several tens to a few hundred volts is applied to the boron layer to accelerate photo-electrons away from the backside surface and create additional electrons by an avalanche effect. Grounded p-wells protect active circuits as needed from the reversed biased epitaxial layer.