公开(公告)号：US20130222013A1

公开(公告)日：2013-08-29

申请号：US13403339

申请日：2012-02-23

申请人： Kai D. Feng ,  Hailing Wang ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Hailing Wang ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H03D13/00

CPC分类号： H03K5/156 ,  H03K5/1534

摘要： A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

摘要翻译： 一种功能单元，包括第一场效应晶体管（FET）器件，第二FET器件，连接到第一FET器件的栅极端子的第一节点和第二FET器件的栅极端子，其中第一节点可操作以接收 来自交流（AC）电压源的电压信号，连接到第一FET器件和第二FET器件的放大器部分，用于接收来自第一FET器件和第二FET器件的信号的放大器部分，相位比较器 部分具有连接到放大器的输出端子的第一输入端子和用于从AC电压源接收电压信号的第二输入端子，该相位比较器部分用于输出指示二进制值的位的电压。

公开(公告)号：US08232115B2

公开(公告)日：2012-07-31

申请号：US12566726

申请日：2009-09-25

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

公开(公告)号：US08493075B2

公开(公告)日：2013-07-23

申请号：US12877159

申请日：2010-09-08

申请人： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： G01R31/00

CPC分类号： H03K19/00369

摘要： An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

摘要翻译： 用于输电线路的嵌入式去耦电容器损耗监测器，可以在任何标准CMOS或BiCMOS电路中集成和制造。 嵌入式噪声监测器用于检测劣化的电容器，并禁止其进一步操作，这将延长电路系统的工作寿命，并防止由于硬击穿（或电容器短路）引起的灾难性故障。 在一个方面，监测电路和方法在灾难性去耦电容器故障之前检测早期劣化信号，并且还可以对劣化的去耦电容进行引脚定位并使其失效，避免去耦电容器击穿故障的影响。 监控电路和方法提供了去耦电容冗余，并且包括用于功能和可靠性的嵌入式和自诊断电路。

公开(公告)号：US20120175612A1

公开(公告)日：2012-07-12

申请号：US13423823

申请日：2012-03-19

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L23/48

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

公开(公告)号：US20120056667A1

公开(公告)日：2012-03-08

申请号：US12877159

申请日：2010-09-08

申请人： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Jong-Ru Guo ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H03K5/00

CPC分类号： H03K19/00369

摘要： An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

摘要翻译： 用于输电线路的嵌入式去耦电容器损耗监测器，可以在任何标准CMOS或BiCMOS电路中集成和制造。 嵌入式噪声监测器用于检测劣化的电容器，并禁止其进一步操作，这将延长电路系统的工作寿命，并防止由于硬击穿（或电容器短路）引起的灾难性故障。 在一个方面，监测电路和方法在灾难性去耦电容器故障之前检测早期劣化信号，并且还可以对劣化的去耦电容进行引脚定位并使其失效，避免去耦电容器击穿故障的影响。 监控电路和方法提供了去耦电容冗余，并且包括用于功能和可靠性的嵌入式和自诊断电路。

公开(公告)号：US20110102005A1

公开(公告)日：2011-05-05

申请号：US12610683

申请日：2009-11-02

申请人： Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

发明人： Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

IPC分类号： G01R31/26 ,  G01R31/3187

CPC分类号： G01R31/2856 ,  G01R31/2875

摘要： An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

摘要翻译： 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。

公开(公告)号：US07671444B2

公开(公告)日：2010-03-02

申请号：US11767580

申请日：2007-06-25

申请人： Ping-Chuan Wang ,  Wai-Kin Li

发明人： Ping-Chuan Wang ,  Wai-Kin Li

IPC分类号： H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

摘要翻译： 本公开总体上涉及集成电路（IC）芯片制造，更具体地，涉及包括开口，层间电介质中的第一通孔和第二通孔的电熔丝装置，其中开口，第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层，其中所述金属层用金属填充所述开口，并且其中所述第一通孔和所述第二通孔基本为空，以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。

公开(公告)号：US20120264295A1

公开(公告)日：2012-10-18

申请号：US13530999

申请日：2012-06-22

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US08158014B2

公开(公告)日：2012-04-17

申请号：US12139722

申请日：2008-06-16

申请人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： C03C15/00 ,  H01L21/31

CPC分类号： G03F7/70466 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24802

摘要： A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

摘要翻译： 在基板上形成具有第二感光性的第二光致抗蚀剂的叠层和具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 通过第一曝光和第一显影在第一光致抗蚀剂中形成第一图案，而下面的第二光致抗蚀剂保持完整。 在第二光致抗蚀剂中形成包括线阵列的第二图案。 在第一光致抗蚀剂的剩余部分下面的第二光致抗蚀剂的暴露部分形成线图案的窄部分，而在光致抗蚀剂的剩余部分的区域外部的第二光致抗蚀剂的暴露部分形成线图案的宽部分 。 线图案的每个宽部分在第二图案中形成凸起，这增加了第二图案和导电通孔图案之间的覆盖公差。

公开(公告)号：US20100118636A1

公开(公告)日：2010-05-13

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L21/44

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。