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    Structure and method to improve ETSOI MOSFETS with back gate
    14.
    发明授权
    Structure and method to improve ETSOI MOSFETS with back gate 有权
    具有后栅的ETSOI MOSFET的结构和方法

    公开(公告)号：US08664050B2

    公开(公告)日：2014-03-04

    申请号：US13424447

    申请日：2012-03-20

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

    摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

    摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 在第一半导体层上形成栅极结构，并且在涉及的湿清洗期间，STI纹路侵蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

    DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE
    16.
    发明申请
    DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE 失效
    用于背盖电极的双深度自对准隔离结构

    公开(公告)号：US20120256260A1

    公开(公告)日：2012-10-11

    申请号：US13082491

    申请日：2011-04-08

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

    摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

    摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

    Dual-depth self-aligned isolation structure for a back gate electrode
    17.
    发明授权
    Dual-depth self-aligned isolation structure for a back gate electrode 失效
    用于背栅电极的双深度自对准隔离结构

    公开(公告)号：US08399957B2

    公开(公告)日：2013-03-19

    申请号：US13082491

    申请日：2011-04-08

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

    摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

    摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

    Semiconductor substrate with transistors having different threshold voltages
    18.
    发明授权
    Semiconductor substrate with transistors having different threshold voltages 失效
    具有不同阈值电压的晶体管的半导体衬底

    公开(公告)号：US08642415B2

    公开(公告)日：2014-02-04

    申请号：US13487511

    申请日：2012-06-04

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

    摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

    SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
    20.
    发明申请
    SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES 失效
    具有不同阈值电压的晶体管的半导体衬底

    公开(公告)号：US20130295730A1

    公开(公告)日：2013-11-07

    申请号：US13487511

    申请日：2012-06-04

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

    摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。