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    Semiconductor device and manufacturing method thereof
    11.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07936016B2

    公开(公告)日：2011-05-03

    申请号：US12413980

    申请日：2009-03-30

    申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    IPC分类号： H01L29/76

    CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

    摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20100230761A1

    公开(公告)日：2010-09-16

    申请号：US12720174

    申请日：2010-03-09

    申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

    摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

    SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR
    14.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR 审中-公开
    包含CMIS晶体管的半导体器件

    公开(公告)号：US20070284671A1

    公开(公告)日：2007-12-13

    申请号：US11759564

    申请日：2007-06-07

    申请人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    发明人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66545

    摘要： Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.

    摘要翻译： 由多晶硅膜制成的栅电极被隔离并且通过填充在NMIS区域和PMIS区域的边界处的隔离绝缘膜上形成的间隙的侧壁间隔部分相互面对。 在一个栅电极上形成第一金属膜，另一个栅电极上形成非均匀的第二金属膜。 通过热处理促进硅化物反应，两个栅电极成为不均匀的金属硅化物栅极。 通过插入作为绝缘膜的侧壁间隔物部分来抑制金属膜从金属膜到栅电极的相互扩散。

    Method of manufacturing a semiconductor memory device
    16.
    发明授权
    Method of manufacturing a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5753527A

    公开(公告)日：1998-05-19

    申请号：US613555

    申请日：1996-03-11

    申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10808

    摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

    摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

    Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer
    17.
    发明授权
    Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer 失效
    在绝缘层中使用钛酸钛酸锂和钛酸钡铁电体的电子器件

    公开(公告)号：US5572052A

    公开(公告)日：1996-11-05

    申请号：US374890

    申请日：1995-01-19

    申请人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

    发明人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

    IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/92 ,  H01L29/94 ,  G11C11/22 ,  H01G4/06 ,  H01G4/20

    CPC分类号： H01L27/11502 ,  H01L29/78391 ,  H01L29/92 ,  H01L29/94

    摘要： In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

    摘要翻译： 在使用锆钛酸铅（PZT）或锆钛酸镧铅（PLZT）作为主要绝缘材料的电子器件中，在主要由钛酸铅，钛酸镧铅，钛酸铅等构成的基础绝缘层上形成PZT膜或PLZT膜， 钛酸钡，钛酸锶，钛酸锶钡，锆酸铅或锆酸镧铅。 在MIS结构中，依次沉积半导体，次绝缘层，PZT膜和金属。 在电容器中，副绝缘层和PZT膜夹在一对电极之间。 亚绝缘层提高了PZT或PLZT的结晶度和介电常数。 可以添加Pb，La，Zr或Ti的氧化物作为副绝缘层，以进一步抑制电流泄漏。