摘要:
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要:
A multi-color document reading apparatus used in a facsimile apparatus for reading a document disposed at a predetermined position containing pictures of multiple colors on a line-by-line basis while discriminately identifying the colors includes an image sensor for sensing optical images in a predetermined area including at least one line of the document disposed at the predetermined position, light sources for selectively illuminating at least the predetermined area in one of first and second energized states differing from each other in respect to the spectral characteristics thereof, a switch circuit for selectively energizing the light sources for illuminating the document in one of the first and second states, a distortion correcting circuit including memories for storing first and second shading waveforms derived from data sensed by the image sensor for optical images of a standard sheet of a specific color disposed at the predetermined position and illuminated by the light source in the first and second energized states, respectively, and a color separating circuit for identifying data of different colors of the multi-color pictures included in one line of the document for generating color-separated signals representing the different colors.
摘要:
Disclosed is a rule management apparatus which acquires a design rule for regulating a part shape from systems such as a CAD system 401, converts the acquired deign rule into data having a hierarchical node format, calculates relationship strength which indicates strength of a relationship between the design rule converted into data having a hierarchical node format and another node, sets to the relationship strength between design rules which are substantially the same but described in different systems to be a maximum value, and stores in an integrating rule DB 300 the relationship strength and the design rules in association with one another.
摘要:
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要:
An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.
摘要:
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要:
Problem to be Solved:To cut down individual development and reduce a design load in image analysis functions with different objects and information to be recognized.Solution:An image analysis device for analyzing information on input moving image to output the results of the analysis includes an individual processing section configured to perform processing according to an object to be analyzed to recognize objects included in the moving image and a common processing section configured to subject a plurality of different objects to be analyzed to a common analysis processing based on the results recognized by the individual processing section, in which the individual processing section includes an information extraction section configured to recognize the object included in the moving image according to the object to be analyzed to extract information, a corresponding information storage section configured to store corresponding information showing to which information processed in the common processing section the extracted information corresponds, and a processing result acquisition section configured to acquire the information analyzed and processed by the common processing section.
摘要:
A design change range determining apparatus assigns a link between the one and another elements to generate link information table regarding the assigned link, and when the element is specified through an input unit, retrieves link information table to obtain the parent node associated with the specified element, obtains a child node associated with the parent node, and further obtains a child node which is a parent node of the obtain child node; and display the obtained parent nodes and child nodes on a display.
摘要:
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要:
In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.