公开(公告)号：US08815721B2

公开(公告)日：2014-08-26

申请号：US12971188

申请日：2010-12-17

申请人： Zachary Matthew Stum ,  Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Almern Losee

发明人： Zachary Matthew Stum ,  Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Almern Losee

IPC分类号： H01L21/425 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/36 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7816 ,  H01L29/7827

摘要： A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

摘要翻译： 一种方法，包括：将掺杂剂类型引入到半导体层中以限定所述半导体层的阱区，所述阱区包括沟道区，并且将掺杂剂类型引入所述阱区以限定与所述阱大致重合的多个注入区 但不包括渠道区域。

公开(公告)号：US08377812B2

公开(公告)日：2013-02-19

申请号：US12483469

申请日：2009-06-12

申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC分类号： H01L21/28

CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US20100200931A1

公开(公告)日：2010-08-12

申请号：US12368498

申请日：2009-02-10

申请人： Kevin Sean Matocha ,  Stephen Daley Arthur ,  Ramakrishna Rao ,  Peter Almern Losee ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Stephen Daley Arthur ,  Ramakrishna Rao ,  Peter Almern Losee ,  Zachary Matthew Stum

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727

摘要： A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.

摘要翻译： 公开了MOSFET器件和用于制造MOSFET器件的方法。 该方法包括提供包括第一导电类型的半导体器件层和在半导体器件层中离子注入第二导电类型的阱结构的半导体器件结构，其中离子注入包括在单个掩模中提供掺杂剂浓度分布 植入序列。

公开(公告)号：US07781312B2

公开(公告)日：2010-08-24

申请号：US11610199

申请日：2006-12-13

申请人： Kevin Sean Matocha ,  Vinayak Tilak ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Vinayak Tilak ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/20

CPC分类号： H01L21/0465 ,  H01L29/66068

摘要： A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

摘要翻译： 公开了一种制造SiC MOSFET的方法。 该方法包括在衬底上生长SiC外延层，平面化SiC外延层以提供平坦化的SiC外延层，以及形成与平坦化的外延层接触的栅极电介质层。

公开(公告)号：US09006027B2

公开(公告)日：2015-04-14

申请号：US13610614

申请日：2012-09-11

申请人： Zachary Matthew Stum ,  Ahmed Elasser ,  Stephen Daley Arthur ,  Stanislav I. Soloviev ,  Peter Almern Losee

发明人： Zachary Matthew Stum ,  Ahmed Elasser ,  Stephen Daley Arthur ,  Stanislav I. Soloviev ,  Peter Almern Losee

IPC分类号： H01L21/00 ,  H01L31/0328 ,  H01L29/06 ,  H01L29/74 ,  H01L29/87 ,  H01L21/02 ,  H01L29/73 ,  H01L29/739 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/0661 ,  H01L21/02107 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/87

摘要： An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.

摘要翻译： 电气装置包括设置在基底层顶部的阻挡层，其中阻挡层和基底层各自是宽带隙半导体，并且阻挡层和基底层在电气装置中形成掩埋结。 该装置包括设置在阻挡层的表面处的端接特征和靠近端接特征设置的填充沟槽。 填充的沟槽延伸穿过阻挡层以到达衬底层并且被配置为将与掩埋结相关联的电势引导到设置在阻挡层表面附近的端接特征以终止掩埋结。

公开(公告)号：US20140070229A1

公开(公告)日：2014-03-13

申请号：US13610614

申请日：2012-09-11

申请人： Zachary Matthew Stum ,  Ahmed Elasser ,  Stephen Daley Arthur ,  Stanislav I. Soloviev ,  Peter Almern Losee

发明人： Zachary Matthew Stum ,  Ahmed Elasser ,  Stephen Daley Arthur ,  Stanislav I. Soloviev ,  Peter Almern Losee

IPC分类号： H01L29/20 ,  H01L21/768 ,  H01L29/161

CPC分类号： H01L29/0661 ,  H01L21/02107 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/87

摘要： An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.

摘要翻译： 电气装置包括设置在基底层顶部的阻挡层，其中阻挡层和基底层各自是宽带隙半导体，并且阻挡层和基底层在电气装置中形成掩埋结。 该装置包括设置在阻挡层的表面处的端接特征和靠近端接特征设置的填充沟槽。 填充的沟槽延伸穿过阻挡层以到达衬底层并且被配置为将与掩埋结相关联的电势引导到设置在阻挡层表面附近的端接特征以终止掩埋结。

公开(公告)号：US20130221374A1

公开(公告)日：2013-08-29

申请号：US13597299

申请日：2012-08-29

申请人： Ramakrishna Rao ,  Stephen Daley Arthur ,  Peter Almern Losee ,  Kevin Sean Matocha

发明人： Ramakrishna Rao ,  Stephen Daley Arthur ,  Peter Almern Losee ,  Kevin Sean Matocha

IPC分类号： H01L29/16

CPC分类号： H01L29/1608 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction.

摘要翻译： 半导体器件包括包含半导体材料的衬底。 衬底具有限定表面法线方向的表面，并且包括PN结，其包括在第一区域和第二区域之间的界面，其中第一（第二）区域包括第一（第二）掺杂剂类型，以便具有第一 （第二）导电类型。 衬底包括邻近P-N结设置并且具有通常为第二掺杂区域中的第二掺杂剂类型的有效浓度的第二掺杂剂类型的有效浓度的终止延伸区域。 衬底包括与表面相邻并且在表面与终止延伸区域的至少一部分之间布置的调节区域，其中当从端接延伸区域沿着表面移动到调节区域中时，第二掺杂剂类型的有效浓度通常降低 正常方向

公开(公告)号：US20110024765A1

公开(公告)日：2011-02-03

申请号：US12533712

申请日：2009-07-31

申请人： Peter Almern Losee ,  Stephen Daley Arthur ,  Dale Marius Brown ,  Kevin Sean Matocha ,  Ravinuthala Ramakrishna Rao

发明人： Peter Almern Losee ,  Stephen Daley Arthur ,  Dale Marius Brown ,  Kevin Sean Matocha ,  Ravinuthala Ramakrishna Rao

IPC分类号： H01L29/12 ,  H01L21/04 ,  H01L29/78

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/1608

摘要： There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts.

摘要翻译： 提供了包括碳化硅（SiC）的半导体结构和器件及其制造方法。 结构和器件包括基底或屏蔽层，通道和表面层，所有这些都希望通过离子注入形成。 结果，本文提供的结构和装置是硬的“常关”装置，即呈现大于约3伏特的阈值电压。

公开(公告)号：US08216370B2

公开(公告)日：2012-07-10

申请号：US11300660

申请日：2005-12-12

申请人： Mark Philip D'Evelyn ,  Thomas Richard Anthony ,  Stephen Daley Arthur ,  Lionel Monty Levinson ,  John William Lucek ,  Larry Burton Rowland ,  Suresh Shankarappa Vagarali

发明人： Mark Philip D'Evelyn ,  Thomas Richard Anthony ,  Stephen Daley Arthur ,  Lionel Monty Levinson ,  John William Lucek ,  Larry Burton Rowland ,  Suresh Shankarappa Vagarali

IPC分类号： C30B21/04

CPC分类号： B01J3/065 ,  B01J3/062 ,  B01J2203/0635 ,  B01J2203/0645 ,  B01J2203/066 ,  B01J2203/0665 ,  B01J2203/067 ,  B01J2203/0675 ,  B01J2203/069 ,  C30B33/00 ,  Y10T117/1004 ,  Y10T117/1008

摘要： A method for removing defects at high pressure and high temperature (HP/HT) or for relieving strain in a non-diamond crystal commences by providing a crystal, which contains defects, and a pressure medium. The crystal and the pressure medium are disposed in a high pressure cell and placed in a high pressure apparatus, for processing under reaction conditions of sufficiently high pressure and high temperature for a time adequate for one or more of removing defects or relieving strain in the single crystal.

摘要翻译： 通过提供含有缺陷的晶体和压力介质，开始在高压高温（HP / HT）下除去非金刚石晶体中的缺陷或解除应变的方法。 将晶体和压力介质设置在高压电池中并放置在高压设备中，用于在足够高的压力和高温的反应条件下进行处理足够的时间以适应一个或多个去除缺陷或减轻单一应变的应变 水晶。

公开(公告)号：US07078731B2

公开(公告)日：2006-07-18

申请号：US11010507

申请日：2004-12-13

申请人： Mark Philip D'Evelyn ,  Dong-Sil Park ,  Steven Francis LeBoeuf ,  Larry Burton Rowland ,  Kristi Jean Narang ,  Huicong Hong ,  Stephen Daley Arthur ,  Peter Micah Sandvik

发明人： Mark Philip D'Evelyn ,  Dong-Sil Park ,  Steven Francis LeBoeuf ,  Larry Burton Rowland ,  Kristi Jean Narang ,  Huicong Hong ,  Stephen Daley Arthur ,  Peter Micah Sandvik

IPC分类号： H01L33/00

CPC分类号： H01L33/32 ,  B82Y10/00 ,  B82Y30/00 ,  C30B7/00 ,  C30B7/005 ,  C30B29/403 ,  C30B29/406

摘要： A GaN crystal having up to about 5 mole percent of at least one of aluminum, indium, and combinations thereof. The GaN crystal has at least one grain having a diameter greater than 2 mm, a dislocation density less than about 104 cm−2, and is substantially free of tilt boundaries.

摘要翻译： 具有至多约5摩尔％的铝，铟及其组合中的至少一种的GaN晶体。 GaN晶体具有至少一个直径大于2mm的晶粒，位错密度小于约10 -4 cm -2，并且基本上没有倾斜边界。