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    Semiconductor memory device
    11.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06208010B1

    公开(公告)日：2001-03-27

    申请号：US08574110

    申请日：1995-12-18

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    IPC分类号： H01L2900

    CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

    摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

    Semiconductor memory device
    12.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06864559B2

    公开(公告)日：2005-03-08

    申请号：US10377717

    申请日：2003-03-04

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/00

    CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

    摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

    Semiconductor memory device having separately biased wells for isolation
    13.
    发明授权
    Semiconductor memory device having separately biased wells for isolation 失效
    半导体存储器件具有单独偏置的阱用于隔离

    公开(公告)号：US5497023A

    公开(公告)日：1996-03-05

    申请号：US352238

    申请日：1994-12-08

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikasu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikasu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

    IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

    摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

    Semiconductor device
    14.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4868626A

    公开(公告)日：1989-09-19

    申请号：US044202

    申请日：1987-04-30

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

    Semiconductor device
    15.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4672416A

    公开(公告)日：1987-06-09

    申请号：US843614

    申请日：1986-03-25

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/02

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。