公开(公告)号：US5440161A

公开(公告)日：1995-08-08

申请号：US273175

申请日：1994-07-26

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Yasuo Inoue ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/108 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L21/265

CPC分类号： H01L29/402 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.

摘要翻译： 在硅衬底1的主表面上形成掩埋氧化膜4.在掩埋氧化物膜4上形成SOI层5.形成分别连接到nMOS 2和pMOS 3的沟道区的沟道停止区22a和22b 在SOI层5的元件隔离区域中，在SOI层的元件形成区域中形成nMOS 2和pMOS 3。 包含在通道停止区域22a和22b中的ap型杂质或n型杂质的浓度高于包含在nMOS 2的沟道区域或pMOS 3的沟道区域中的p型杂质或n型杂质的浓度。 FS沟道栅极16形成在通道阻挡区域22a和22b上，其中FS栅氧化膜15插入其间。 因此，可以获得具有SOI结构的半导体器件，该半导体器件能够通过有效地抽出存储在晶体管的沟道区域中的过多的载流子来抑制寄生双极性操作。

公开(公告)号：US5413968A

公开(公告)日：1995-05-09

申请号：US22876

申请日：1993-02-25

申请人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/11 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14). This semiconductor device is manufactured by depositing the insulator layer (5, 15) having the contact hole (6, 9) on the conductor layer (3, 7) having the silicon crystal, forming the barrier layer (14) and the polysilicon layer (7, 10) overlapping each other in the contact hole (6, 9) and on the insulator layer (5, 15) and then patterning these overlapping barrier layer (14) and polysilicon layer (7, 10), forming a metal layer (8, 11) thereon to be silicidized, and removing unreacted metal. The semiconductor device thus manufactured prevents a suction of silicon from the conductor layer (3, 7) to the metal silicide layer (12) and hence prevents an increase in resistance value due to a deficiency of silicon produced in the conductor layer (3, 7), thereby minimizing a series resistance of the metal silicide layer (12), a contact portion and the conductor layer (3, 7).

摘要翻译： 半导体器件包括具有硅晶体的导体层（3,7），形成在导体层（3,7）的表面上的绝缘体层（5,15），其具有穿过其的导体层的所述表面的接触孔 （3,7），形成在所述绝缘体层（5,15）中的预定位置处并具有其底表面成为所述导体层（3,7）的表面的接触孔（6,9）的互连部分， 至少在所述互连部分中的所述导体层（3,7）的表面上形成在所述接触孔的底部处的阻挡层（14）和形成在所述阻挡层（14）上的金属硅化物层（12） 。 该半导体器件通过在具有硅晶体的导体层（3,7）上沉积具有接触孔（6,9）的绝缘体层（5,15），形成阻挡层（14）和多晶硅层（ 7,10）在接触孔（6,9）和绝缘体层（5,15）上彼此重叠，然后对这些重叠的阻挡层（14）和多晶硅层（7,10）进行构图，形成金属层 8,11）在其上被硅化，并除去未反应的金属。 这样制造的半导体器件防止硅从导体层（3,7）吸收到金属硅化物层（12），从而防止由于导体层（3,7）中产生的硅的缺陷导致的电阻值增加 ），从而使金属硅化物层（12），接触部分和导体层（3,7）的串联电阻最小化。

公开(公告)号：US5094714A

公开(公告)日：1992-03-10

申请号：US607800

申请日：1990-10-31

申请人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  C30B13/00 ,  H01L21/762

CPC分类号： C30B29/06 ,  C30B13/00 ,  H01L21/76297 ,  Y10T428/31504

摘要： A wafer structure for forming a semiconductor single crystal film comprises a semiconductor single crystal substrate, a plurality of recesses formed in a grooved shape to one main surface of the semiconductor single crystal substrate, insulation material embedded to the inside of these recesses, an insulation layer deposited over the insulation material and the semiconductor single crystal substrate and integrated with the insulation material and a polycrystalline or amorphous semiconductor layer to be recrystallized disposed over the insulation layer.A wafer structure with no or less grain boundaries can be obtained. Further, polycrystalline or amorphous semiconductor layer can be prevented from peeling off the substrate by the additional layering of a protecting insulation layer.

摘要翻译： 用于形成半导体单晶膜的晶片结构包括半导体单晶衬底，形成为半导体单晶衬底的一个主表面的沟槽形状的多个凹槽，嵌入到这些凹部内部的绝缘材料，绝缘层 沉积在绝缘材料和半导体单晶衬底上并与绝缘材料一体化，并且将多晶或非晶半导体层重结晶设置在绝缘层上。 可以获得没有或没有晶界的晶片结构。 此外，通过附加的保护绝缘层的分层，可以防止多晶或非晶半导体层从基板上剥离。

公开(公告)号：US4822752A

公开(公告)日：1989-04-18

申请号：US022717

申请日：1987-03-06

申请人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/822 ,  H01L29/04 ,  H01L21/306 ,  H01L21/326 ,  H01L21/479

CPC分类号： H01L21/8221 ,  H01L21/2026 ,  H01L21/268 ,  H01L29/045 ,  Y10S117/904 ,  Y10S148/09 ,  Y10S148/091 ,  Y10S148/093

摘要： Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film to melt the polycrystalline or amorphous semiconductor and scanning the energy beam in a predetermined direction such that the direction of the crystal of the semiconductor re-solidified and converted into a single crystal accords with a {111} plane, to produce the single crystal of the semiconductor device. Also disclosed is a semiconductor device produced by the method, which comprises a single crystal layer having a wide range of a crystal in a predetermined direction relative to the facial orientation of the major surface of the substrate, and has a three-dimensional semiconductor circuit element construction.

摘要翻译： 本发明公开了一种制造半导体器件的单晶层的方法，其包括以下步骤：在立方晶系的单晶半导体衬底的主表面上提供由用于接种的开口部分开的氧化物绝缘体层，提供 在包括开口部分的绝缘体层的整个表面上的多晶或非晶半导体层，然后提供保护层，该保护层至少包括反射膜或防反射膜，该反射膜或抗反射膜包括相对于开口的预定方向的预定宽度的条 部分并且以预定间隔，保护层能够控制对应于条纹的部分或不对应于条纹的部分的半导体层中的温度分布，从而完成用于制造半导体器件的基底，之后， 用能量束通过条纹反射照射基座 或抗反射膜，以熔化多晶或非晶半导体并沿预定方向扫描能量束，使得半导体晶体的方向重新固化并转换成单晶符合{111}面，以产生 半导体器件的单晶。 还公开了一种通过该方法制造的半导体器件，该半导体器件包括相对于衬底的主表面的面取向在预定方向上具有宽范围的晶体的单晶层，并且具有三维半导体电路元件 施工。

公开(公告)号：US06198134B1

公开(公告)日：2001-03-06

申请号：US09056616

申请日：1998-04-08

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2701

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US5937284A

公开(公告)日：1999-08-10

申请号：US979621

申请日：1997-11-28

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： H01L27/12 ,  H01L21/00 ,  H01L21/425 ,  H01L21/76

CPC分类号： H01L27/1203

摘要： Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

摘要翻译： 防止有源层边缘中的寄生晶体管的产生。 在绝缘膜（20）上的半导体层（21）的NMOS区域中，使用氮化膜（23）和抗蚀剂（253a）作为掩模，通过旋转倾斜注入注入硼离子。 在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。 在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子可能不被吸入氧化膜中。

公开(公告)号：US5801080A

公开(公告)日：1998-09-01

申请号：US837959

申请日：1997-04-14

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/482 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US5652454A

公开(公告)日：1997-07-29

申请号：US675510

申请日：1996-07-03

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/482 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US5381235A

公开(公告)日：1995-01-10

申请号：US990460

申请日：1992-12-15

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： G01B11/24 ,  G01B11/02 ,  G01B11/25 ,  G01C3/06 ,  H01L27/14

CPC分类号： G01B11/024 ,  G01B11/2518

摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.

摘要翻译： 本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。 三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统， 由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于 与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷 扫描完成，从而提供对象的三维形状。 由此，可以高精度地测量物体的三维形状。

公开(公告)号：US5283455A

公开(公告)日：1994-02-01

申请号：US911582

申请日：1992-07-10

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/6675 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78642

摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

摘要翻译： 在绝缘基板上形成的栅电极的上表面上形成上绝缘层。 栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。 在栅极绝缘层的表面上形成半导体层。 在半导体层中形成三个源/漏区。 沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。 源极/漏极区域布置在两个沟道区域的两端。 每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。