公开(公告)号：US06008510A

公开(公告)日：1999-12-28

申请号：US865328

申请日：1997-05-29

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L21/82 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12 ,  H01L27/105

CPC分类号： H01L27/0218 ,  H01L27/11807

摘要： A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a two-input NAND gate and a diode forward biased between one of power supply lines and the NAND gate. The diode has a P-N junction extending between the top surface of a semiconductor layer and the insulator layer underlying the semiconductor layer. The diode reduces the supply voltage by the forward drop voltage thereof to reduce power consumption in the NAND gate, and the SOI structure of the basic cell prevents reduction of integration density and operational speed.

摘要翻译： 主分片半导体IC具有在SOI衬底上以矩阵形式布置的SOI衬底和多个基本单元。 基本单元包括双输入NAND门和正向偏置在电源线和NAND门之一之间的二极管。 二极管具有在半导体层的顶表面和半导体层下面的绝缘体层之间延伸的P-N结。 二极管通过其正向下降电压来降低电源电压以降低与非门的功耗，并且基本单元的SOI结构防止集成密度和操作速度的降低。

公开(公告)号：US5397906A

公开(公告)日：1995-03-14

申请号：US39742

申请日：1993-03-30

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10 ,  H01L27/02

CPC分类号： H01L27/11896

摘要： In an unused unit cell of a gate array integrated semiconductor device, a P-type semiconductor region is connected to a ground potential connection and an N-type semiconductor region is connected to a positive power supply connection, thereby reversely-biasing the P-type and N-type semiconductor regions.

摘要翻译： 在门阵列集成半导体器件的未使用的单元中，P型半导体区域连接到地电位连接，并且N型半导体区域连接到正电源连接，由此反向偏置P型 和N型半导体区域。

公开(公告)号：US06414357B1

公开(公告)日：2002-07-02

申请号：US09655940

申请日：2000-09-06

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L2701

CPC分类号： H01L27/11807

摘要： Disclosed is a method for making a semiconductor integrated circuit device used to form a p-channel MOS field-effect transistor and a n-channel MOS field-effect transistor on a common SOI substrate with a structure that a first silicon layer, insulating film and a second silicon layer are layered; wherein the steps from sectioning a SOI layer as the second silicon layer by insulation separation into a plurality of active regions to forming at least one gate electrode to be laid through gate insulating film on the surface of each of the plurality of active regions are conducted with no relation to the conductivity type of MOS field-effect transistor.

摘要翻译： 公开了一种制造用于在公共SOI衬底上形成p沟道MOS场效应晶体管和n沟道MOS场效应晶体管的半导体集成电路器件的方法，其结构为：第一硅层，绝缘膜和 层叠第二硅层; 其中通过绝缘分离将SOI层作为第二硅层分离成多个有源区域以形成要在多个有源区域中的每一个的表面上铺设通过栅极绝缘膜的至少一个栅电极的步骤是用 与MOS场效应晶体管的导电类型无关。

公开(公告)号：US06243284B1

公开(公告)日：2001-06-05

申请号：US09498115

申请日：2000-02-04

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： G11C1700

CPC分类号： G11C17/12 ,  G11C7/18 ,  G11C11/5692 ,  G11C16/24 ,  G11C2211/5617

摘要： A multivalued mask ROM is configured by arranging cell transistors in a matrix form, which is defined by wiring word lines and ground lines in rows and by wiring bit lines in columns. Each of the cell transistors is encompassed by a word line, a ground line and at least two bit lines. Herein, gates of the cell transistors which align in a same row are connected with a same word line, while sources and drains of the cell transistors are adequately connected or disconnected with the ground line and bit lines. In an integrated circuit, contacts are formed between n+ regions, first-layer metal and second-layer metal on a well region to establish connections by which the source and drain of the cell transistor are adequately connected with the ground line and/or bit lines. That is, ROM codes are formed using the contacts. A circuitry is provided for the multivalued mask ROM to read out stored information of the cell transistors in synchronization with a clock signal. In Low-level duration of the clock signal, the circuitry performs precharge to a first bit line and pull-down to a second bit line. In High-level duration of the clock signal, the circuitry stops the precharge and pull-down while activating the word line to detect levels of the first and second lines, which are used as values for a two-bit code corresponding to stored information of the cell transistor.

摘要翻译： 通过以矩阵形式布置单元晶体管来配置多值掩模ROM，该矩阵形式由布线字线和地线在行中以及列中的布线位线限定。 每个单元晶体管被字线，接地线和至少两个位线包围。 这里，排列在相同行中的单元晶体管的栅极与相同的字线连接，而单元晶体管的源极和漏极与接地线和位线充分连接或断开。 在集成电路中，在阱区上的n +区，第一层金属和第二层金属之间形成接触，以建立连接，通过该连接，单元晶体管的源极和漏极与地线和/或位线充分连接 。 也就是说，使用触点形成ROM代码。 为多值掩模ROM提供电路，以与时钟信号同步地读出存储的单元晶体管的信息。 在时钟信号的低电平持续时间内，电路对第一位线进行预充电，并下拉到第二位线。 在时钟信号的高电平持续时间中，电路在激活字线时停止预充电和下拉，以检测第一和第二线的电平，其被用作对应于存储的信息的两位代码的值 单元晶体管。

公开(公告)号：US06208171B1

公开(公告)日：2001-03-27

申请号：US09294089

申请日：1999-04-19

申请人： Kouichi Kumagai ,  Susumu Kurosawa

发明人： Kouichi Kumagai ,  Susumu Kurosawa

IPC分类号： H03K1920

CPC分类号： H03K19/0016

摘要： In a semiconductor integrated circuit, a control transistor 4 and a potential clamp circuit 9 are arranged between a power supply line 2 and a virtual power supply line 3. Even in a sleeve mode where the control transistor 4 is turned off, the potential clamp circuit 9-1 clamps the virtual power supply line 3 at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor 4 can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

摘要翻译： 在半导体集成电路中，控制晶体管4和电位钳位电路9配置在电源线2和虚拟电源线3之间。即使在控制晶体管4截止的套管模式中，电位钳位电路 9-1将虚拟电源线3夹在一定电位以保持逻辑电路的每个节点的电位状态（高电平或低电平）。 此时，形成逻辑电路的每个FET被施加反偏压，使得阈值电压Vt变得高于活动模式中的阈值电压。 因此，可以降低泄漏电流。 在半导体集成电路中，可以选择控制晶体管4的阈值电压Vt等于形成逻辑电路的互补FET的一个FET的阈值电压Vt。 因此，可以减少布局区域和制造步骤的数量。

公开(公告)号：US5561388A

公开(公告)日：1996-10-01

申请号：US331968

申请日：1994-10-31

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H03K19/01 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/08

CPC分类号： H03K19/017518 ,  H03K19/01806 ,  H03K19/018521

摘要： In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and a second power supply voltage, and the CMOS circuit and a level conversion circuit between a CMOS level and a bipolar level are operated between the first power supply voltage and a third power supply voltage. The third power supply voltage is between the first and second power supply voltages.

摘要翻译： 在CMOS电路和双极电路混合的半导体器件中，双极电路在第一电源电压和第二电源电压之间运行，CMOS电路和CMOS电平和双极电平之间的电平转换电路 在第一电源电压和第三电源电压之间运行。 第三电源电压在第一和第二电源电压之间。

公开(公告)号：US06188111B1

公开(公告)日：2001-02-13

申请号：US09052157

申请日：1998-03-31

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L2974

CPC分类号： H01L29/78648 ,  H01L27/1203

摘要： In a semiconductor device including a MOSFET, a first semiconductor layer is formed over a silicon substrate and has a gate region. Further, a second semiconductor layer is formed over the first semiconductor layer with a gate oxide film therebetween, and has an active region. The active region has a source region, a drain region and a channel region. An insulator layer on the active region encloses a back gate wiring layer.

摘要翻译： 在包括MOSFET的半导体器件中，在硅衬底上形成第一半导体层并具有栅极区域。 此外，在第一半导体层上形成第二半导体层，其间具有栅极氧化膜，并且具有有源区。 有源区具有源极区，漏极区和沟道区。 有源区上的绝缘体层包围一个背栅极布线层。

公开(公告)号：US5608240A

公开(公告)日：1997-03-04

申请号：US347517

申请日：1994-11-30

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L21/8238 ,  H01L21/82 ,  H01L27/092 ,  H01L27/118 ,  H01L27/10

CPC分类号： H01L27/11807

摘要： The invention provides a semiconductor integrated circuit including a substrate, and a plurality of block cells arranged on the substrate and including a plurality of basic cells. Each of the basic cells includes a plurality of CMOS transistors. At least one of the CMOS transistors is an asymmetrical one in which one of a source diffusion layer or a drain diffusion layer has a lightly doped drain (LDD) structure or a deep doped drain (DDD) structure.

摘要翻译： 本发明提供了一种半导体集成电路，其包括衬底和布置在衬底上并包括多个基本单元的多个块单元。 每个基本单元包括多个CMOS晶体管。 至少一个CMOS晶体管是不对称的，其中源极扩散层或漏极扩散层之一具有轻掺杂漏极（LDD）结构或深掺杂漏极（DDD）结构。

公开(公告)号：US08610141B2

公开(公告)日：2013-12-17

申请号：US13640869

申请日：2011-04-14

申请人： Naoya Tohyama ,  Takuya Inoue ,  Kouichi Kumagai ,  Takaha Kunieda

发明人： Naoya Tohyama ,  Takuya Inoue ,  Kouichi Kumagai ,  Takaha Kunieda

IPC分类号： H01L33/08 ,  H01L33/64 ,  H01L33/62

CPC分类号： H01L25/167 ,  F21K9/23 ,  F21V3/00 ,  F21Y2115/10 ,  H01L33/648 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3025 ,  H05K1/0201 ,  H05K1/0203 ,  H05K1/0306 ,  H05K1/144 ,  H05K3/0061 ,  H05K2201/062 ,  H05K2201/10106 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.

摘要翻译： 本发明包括一个或多个LED元件，通过微型凸块安装LED元件的硅衬底，并且内部形成的布线连接到微型突起，与LED元件的相对侧粘贴的隔热有机衬底， 硅基板的安装侧，并且具有布线穿过的通孔，粘贴在隔热有机基板的硅基板侧的相反侧的芯片安装基板和内部形成的布线连接到布线 隔热有机基板的通孔，以及通过微型突起与芯片安装基板的布线连接的LED控制电路芯片，并且经由隔热有机基板侧的相反侧的微凸块安装 的芯片安装基板。

公开(公告)号：US6057568A

公开(公告)日：2000-05-02

申请号：US719203

申请日：1996-09-25

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L27/092 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/118 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11807

摘要： A semiconductor integrated circuit is disclosed which avoids operating speed degradation resulting from an increase of the gate resistance due to making the size of the device small. In a basic cell 103 comprising a group 101 of P-channel MOS transistors and a group 102 of N-channel MOS transistors, the gate width of all the MOS transistors constituting the basic cell 103 is set below 7 .mu.m, and the gate electrodes 108a, 108b, 109a, 109b are formed to surround the perimeter of source or drain diffusion areas 106a, 106c, 107a, 107c of the MOS transistors to form an electrically closed loop.

摘要翻译： 公开了一种半导体集成电路，其避免了由于使器件的尺寸较小而导致的栅极电阻增加导致的工作速度劣化。 在包括P沟道MOS晶体管的组101和N沟道MOS晶体管的组102的基本单元103中，构成基本单元103的所有MOS晶体管的栅极宽度被设定为低于7μm，栅电极 108a，108b，109a，109b形成为围绕MOS晶体管的源极或漏极扩散区域106a，106c，107a，107c的周边以形成电闭环。