Abstract:
A pulse controller with dual latches includes a first latch unit and a second latch unit, in which two latch units are used to latch signal level for ensuring a sufficient conducting amount of the switching element in the rear end power output unit, and through a mutual interaction between the first and the second latch units, a complementary turning-on and turning-off situation therebetween is formed, and further, the signal from a trigger signal source and the feedback from the power output unit are employed to generate the duty cycle signal for the power output unit so as to replace the conventional pulse width modulation circuit.
Abstract:
A switch control circuit for controlling a first switch element and a second switch element within a bridgeless switching circuit is provided. The bridgeless switching circuit generates an output signal according to an alternating current signal. The switch control circuit includes a current generating element and a phase generating element. The current generating element is for sensing a first current flowing through the first switch element and a second current flowing through the second switch element, and generating a phase comparison result according to the first and the second currents. The phase generating element generates a first control signal and a second control signal according to a power factor correction signal and the phase comparison result to control conducting status of the first and the second switch elements, respectively.
Abstract:
A flyback circuit providing synchronized control includes a pulse width modulation (PWM) unit, a synchronized control unit and an ON period limiting unit. The PWM unit generates a driving signal to control a switch ON period of a primary winding and provides a synchronized signal prior to the generation of the driving signal that has output time series ahead the driving signal. The synchronized control unit receives the synchronized signal through an induction winding to set off a synchronized commutation switch. The ON period limiting unit starts a period limiting time series after the synchronized commutation switch has been set on. After the synchronized commutation switch is set off by the synchronized signal the ON period limiting unit is reset to an initial condition. The synchronized commutation switch maintains an ON condition until the period limiting time series end, then the ON period limiting unit generates a forced ending signal to set off the synchronized commutation switch so that the flyback circuit maintains operation at a minimum duty frequency.
Abstract:
The present invention discloses a method and a circuit for controlling a start-up cycle of an integrated circuit in a circuit system. The method and circuit determine whether or not an input power of the circuit system and a bias voltage power of the integrated circuit have reached a normal operating voltage range to control the bias voltage power to produce a start-up cycle of the integrated circuit. The method and circuit also provides a protection mechanism for an overload of the circuit system overload, so that the integrated circuit can moderate surges and prevent damages.
Abstract:
A flyback converter having an active snubber includes a transformer to receive input power. The transformer has a primary winding at a first side. The active snubber is coupled in parallel with two ends of the primary winding and has a first circumferential circuit coupling in parallel with the primary winding, a second circumferential circuit and a zero voltage switch unit. The second circumferential circuit is controlled by the zero voltage switch unit and incorporated with the first circumferential circuit to form double damping paths to reduce current and prevent resonance that might otherwise occur to a single circumferential circuit and the secondary side of the transformer.
Abstract:
The present invention discloses a variable-frequency circuit with a compensation mechanism, which comprises: a load sensing/decision unit, a frequency-division unit and a level modulation unit. The present invention applies to a power supply having a frequency-division mode. The power supply has a feedback unit generating a feedback signal. The load sensing/decision unit determines the operational mode according to the feedback signal. The frequency-division unit generates a reference frequency signal. The level modulation unit generates a reference level signal. During frequency variation, the level modulation unit generates a compensation current to modulate the reference level signal. Thereby, the PWM unit of the power supply can adjust the working cycle of the power supply according to the reference frequency signal, the reference level signal and the feedback signal.
Abstract:
A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the same power supply to reduce loss of external sampling.
Abstract:
A cycle modulation circuit for limiting voltage peak value of a power supply employed an active clamp. The power supply receives an input power which is modulated through a power driving unit to become a driving power transformed through a transformer to be output. The cycle modulation circuit includes a comparison unit and a linear voltage generation unit. The comparison unit receives the input power to generate a level signal which is used as a base value to compare level with an oscillation signal generated by the linear voltage generation unit, thereby to modulate and output a pulse width limit signal with a composite cycle consisting of a high level and a low level. The pulse width limit signal is input to the power driving unit to limit the peak value of the driving power modulated by the power driving unit.
Abstract:
A snubber circuit includes: at least one impedance component, a capacitor, and a Bipolar Junction Transistor (BJT). The snubber circuit is utilized for protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency. In particular, the at least one impedance component in the snubber circuit can be at least one zener diode, where regarding protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency, the performance of the snubber circuit in a situation where the zener diode is utilized is better than that of the snubber circuit in a situation where other types of impedance components are utilized. An associated method of using a BJT in a snubber circuit is also provided.
Abstract:
A pulse controller with dual latches includes a first latch unit and a second latch unit, in which two latch units are used to latch signal level for ensuring a sufficient conducting amount of the switching element in the rear end power output unit, and through a mutual interaction between the first and the second latch units, a complementary turning-on and turning-off situation therebetween is formed, and further, the signal from a trigger signal source and the feedback from the power output unit are employed to generate the duty cycle signal for the power output unit so as to replace the conventional pulse width modulation circuit.