公开(公告)号：US20160072650A1

公开(公告)日：2016-03-10

申请号：US14479278

申请日：2014-09-06

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Sunil Srinivasa ,  Vladimir Sindalovsky ,  Amaresh V. Malipatil ,  Pervez M. Aziz

IPC: H04L25/06 ,  H04L7/00

CPC classification number: H04L25/06 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0278 ,  H04L25/0292

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts termination impedance automatically to obtain a tuned termination. The termination adaptation is realized with a ‘biased’ bang-bang phase detector (BBPD) that biases the weights applied to UP and DOWN outputs of the phase detector. Through an optimization process, the system locks to data eye corners, and thereby is able to optimize termination though a predetermined criteria, such as signal to noise ratio (SNR), horizontal eye (H-) margin, vertical eye (V-) margin or joint SNR and H-/V-margin optimization. As part of the receiver equalization, adaptive termination tuning is performed after the SerDes receiver (RX) path is initially powered-up by tuning the termination above and below its current initial setting and performing the optimization process.

Abstract translation: 描述的实施例在SerDes设备中提供自适应调整终止阻抗以获得调谐终端的适配过程。 终端适配通过偏置的砰 - 相位相位检测器（BBPD）来实现，该相位检测器偏置施加到相位检测器的UP和DOWN输出的权重。 通过优化过程，系统锁定到数据眼角，从而能够通过诸如信噪比（SNR），水平眼（H）边缘，垂直眼（V-）边缘等预定标准来优化终止 或联合SNR和H / V边缘优化。 作为接收机均衡的一部分，在SerDes接收机（RX）路径最初上电之后，通过调谐高于和低于其当前初始设置的终止并执行优化过程来执行自适应终止调谐。

公开(公告)号：US20140169426A1

公开(公告)日：2014-06-19

申请号：US13719954

申请日：2012-12-19

Applicant: LSI CORPORATION

Inventor： Pervez M. Aziz ,  Hiroshi Kimura

IPC: H04L25/03

CPC classification number: H04L25/03 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/195 ,  H03F2201/3212 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an input coupled to the first input of the subtractor. The weighting circuit, responsive to a weighting coefficient, is coupled between an output of the function circuit and the second input of the first subtractor. The function generator has a transfer function with a third-power term and the weighting coefficient is set to a value based on the level of the signal peaks that will least partially reduce distortion in signals on the output of the subtractor.

Abstract translation: 包含产生失真的模拟电路的接收器，耦合到模拟电路的输出的失真补偿电路以及耦合到失真补偿电路的作为信号峰值检测器操作的限幅器。 失真补偿电路具有减法器，函数发生器和加权电路。 减法器具有耦合到模拟电路的输出的第一输入，第二输入和输出。 函数发生器具有耦合到减法器的第一输入的输入。 响应于加权系数的加权电路耦合在功能电路的输出和第一减法器的第二输入之间。 函数发生器具有具有第三功率项的传递函数，并且加权系数被设置为基于将最小程度地减少减法器的输出上的信号中的失真的信号峰值的电平的值。

公开(公告)号：US09294314B2

公开(公告)日：2016-03-22

申请号：US14228913

申请日：2014-03-28

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Pervez M. Aziz ,  Ye Liu

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04L25/03057 ,  H04L7/10 ,  H04L25/03063 ,  H04L27/0002 ,  H04L2025/03636

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限，并在其中对切片数据进行采样提供更大的定时余量。

公开(公告)号：US20150381393A1

公开(公告)日：2015-12-31

申请号：US14315759

申请日：2014-06-26

Applicant: LSI Corporation

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L25/03 ,  H04L7/033 ,  H04L25/02

CPC classification number: H04L25/03057 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0292 ,  H04L25/0307 ,  H04L25/03159 ,  H04L25/03885 ,  H04L2025/03636 ,  H04L2025/037

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。

公开(公告)号：US20150103961A1

公开(公告)日：2015-04-16

申请号：US14053069

申请日：2013-10-14

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Pervez M. Aziz

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04B1/10 ,  H04B1/30 ,  H04L7/0016 ,  H04L7/0278 ,  H04L25/03038

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.

Abstract translation: 一种在数据接收机等中使用的频带估计器，用于增强接收机中的时钟和数据恢复装置（CDR）的正弦抖动容限。 检测器使用两个不同抽头长度的移动平均滤波器，其接收来自CDR内的增益控制信号。 来自移动平均滤波器的输出信号被处理以通过测量在每个输出信号的转换之间发生的数字时钟周期来确定每个输出信号的半波时间周期。 将最长半波周期的时钟周期数与表示各种频带的频率限制的多个值进行比较，以确定哪个频带将抖动分类为增益控制信号。 确定的频带用于从查找表中选择一组用于CDR中的增益值。

公开(公告)号：US20140169440A1

公开(公告)日：2014-06-19

申请号：US13717973

申请日：2012-12-18

Applicant: LSI CORPORATION

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L27/01 ,  H04L27/00

CPC classification number: H04L25/063

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈回路中的控制器取消，以根据数据判定误差信号或用于停机恢复的定时信号产生补偿信号。