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11.发明授权公开(公告)号：US06545622B1
公开(公告)日：2003-04-08
申请号：US10001628
申请日：2001-10-25
IPC分类号： H03M166
CPC分类号： H04B3/145 , H04L25/03885
摘要： A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a current steering digital to analog converter capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.
摘要翻译： 公开了一种低功耗模拟均衡器，其在单级模拟信号均衡中提供高达二十分贝（20dB）的交流增益。 模拟均衡器包括耦合到两个半电路的运算放大器。 每个半电路包括能够接收模拟输入电压并产生与频率成反比的电流信号的阻抗网络，能够调节运算放大器的增益的电流导向数模转换器，以及耦合的晶体管和放大器 在串联配置中，在阻抗网络的输出处创建一个低阻抗节点。 模拟均衡器采用0.18微米CMOS技术制造，工作电压为1.8伏。
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公开(公告)号：US5541602A
公开(公告)日：1996-07-30
申请号：US451682
申请日：1995-05-26
申请人： Ion E. Opris , Laurence D. Lewicki
发明人： Ion E. Opris , Laurence D. Lewicki
CPC分类号： H03M1/44
摘要： An analog to digital converter stage that has a very short sampling phase settling time requirement is used in a multistage pipelined analog to digital converter with a novel clocking design. Each clock period has a sampling phase and a hold phase. According to a first aspect, the sampling phase of each clock cycle is much shorter than the hold phase. This takes advantage of the reduced sampling phase settling time requirement of the analog to digital converter stage according to the present invention, and also allows a relatively longer hold phase during each clock cycle. The analog to digital converter stage according to the present invention is implemented with an operational amplifier such that during the sampling phase, the operational amplifier does not have to settle in order for correct sampling to occur, whereas operational amplifier settling is required during the hold phase. According to a second aspect, several clocks are cyclicly recirculated among the stages of a pipelined analog to digital converter.
摘要翻译： 具有非常短的采样相位建立时间要求的模数转换器级用于具有新颖时钟设计的多级流水线模数转换器。 每个时钟周期都有一个采样相位和一个保持相位。 根据第一方面，每个时钟周期的采样相位比保持阶段短得多。 这利用了根据本发明的模数转换器级的降低的采样相位稳定时间要求，并且还允许在每个时钟周期期间相对较长的保持相位。 根据本发明的模/数转换器级用运算放大器来实现，使得在采样阶段期间，运算放大器不必为了进行正确的采样而安定运算放大器，而在保持阶段需要运算放大器稳定 。 根据第二方面，几个时钟在流水线模数转换器的级之间循环再循环。
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公开(公告)号：US08588289B2
公开(公告)日：2013-11-19
申请号：US13183932
申请日：2011-07-15
IPC分类号： H03H7/40
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.
摘要翻译： 通过提供并联可控直流和交流信号增益的多个串联耦合级，提供了跨越所有阶段的粗略和精细增益控制，用于自适应信号均衡的粗略和精细升压控制电路。
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公开(公告)号：US20120188014A1
公开(公告)日：2012-07-26
申请号：US13183932
申请日：2011-07-15
IPC分类号： H03F3/45
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.
摘要翻译： 通过提供并联可控直流和交流信号增益的多个串联耦合级，提供了跨越所有阶段的粗略和精细增益控制，用于自适应信号均衡的粗略和精细升压控制电路。
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15.发明授权System and method for providing a parameterized analog feedback loop for continuous time adaptive equalization incorporating low frequency attenuation gain compensation 有权用于提供用于连续时间自适应均衡的参数化模拟反馈回路的系统和方法，其包括低频衰减增益补偿公开(公告)号：US07778323B1
公开(公告)日：2010-08-17
申请号：US11044988
申请日：2005-01-27
IPC分类号： H03H7/30
CPC分类号： H04L25/03038
摘要： A system and a method are disclosed for providing a parameterized analog feedback loop for continuous time adaptive equalization that incorporates low frequency attenuation gain compensation. N adaptive equalizer stages are coupled in series and a slicer circuit is coupled to the last (Nth) adaptive equalizer stage. A single equalizer adaptation control loop controls the frequency response of the adaptive equalizer stages to compensate for the attenuation of a lossy channel. The single equalizer adaptation control loop also compensates for the direct current (DC) loss in the lossy channel by modulating a bias current in the slicer circuit to scale the low frequency feedback with adaptation coefficients that correlate with channel length.
摘要翻译： 公开了一种系统和方法，用于提供用于连续时间自适应均衡的参数化模拟反馈环路，其包括低频衰减增益补偿。 N个自适应均衡器级串联耦合，并且限幅电路耦合到最后（第N个）自适应均衡器级。 单个均衡器适配控制环路控制自适应均衡器级的频率响应以补偿有损信道的衰减。 单个均衡器自适应控制环路还通过调制限幅器电路中的偏置电流来补偿有损信道中的直流（DC）损耗，以便通过与信道长度相关的适配系数来缩放低频反馈。
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16.发明授权System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator 有权用于提供用于与调节单端相位内插器的串行链路的低抖动数据接收器的系统和方法公开(公告)号：US07233173B1
公开(公告)日：2007-06-19
申请号：US10973743
申请日：2004-10-26
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/02 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/222 , H03K3/356034 , H03K3/356086 , H03K5/003 , H03K5/082
摘要： A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.
摘要翻译： 公开了一种用于提供包括低抖动数据接收器的时钟和数据恢复电路的系统和方法。 低抖动数据接收机包括相位内插器，放大器单元和数据采样比较器。 相位内插器和放大器单元为数据采样比较器提供相对免受电源噪声的单端时钟信号。 数据采样比较器由于电源噪声而以最小的抖动对输入数据流进行采样。 数据采样比较器消耗的静态功耗比电流模式逻辑D触发器少，并且还具有与互补金属氧化物半导体（CMOS）逻辑兼容的输出电平。
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公开(公告)号：US06937104B1
公开(公告)日：2005-08-30
申请号：US10668364
申请日：2003-09-22
CPC分类号： H03F3/68 , H03F3/345 , H03F3/347 , H03F2200/72
摘要： An operational amplifier having a low impedance input and a high current gain output. The operational amplifier comprises: 1) a first N-channel transistor having a source coupled to the low impedance input of the operational amplifier; 2) a first constant current source coupled between the source of the first N-channel transistor and ground; 3) a first amplifier stage having an input coupled to the first N-channel transistor source and an inverting output coupled to a gate of the first N-channel transistor; 4) a second amplifier stage having an input coupled to a drain of the first N-channel transistor and an output coupled to the high current gain output of the operational amplifier; and 5) an internal compensation capacitor coupled between the input and the output of the second amplifier stage.
摘要翻译： 具有低阻抗输入和高电流增益输出的运算放大器。 运算放大器包括：1）具有耦合到运算放大器的低阻抗输入的源极的第一N沟道晶体管; 2）耦合在第一N沟道晶体管的源极与地之间的第一恒流源; 3）具有耦合到第一N沟道晶体管源的输入端和耦合到第一N沟道晶体管的栅极的反相输出的第一放大器级; 4）第二放大器级，其具有耦合到第一N沟道晶体管的漏极的输入端和耦合到运算放大器的高电流增益输出的输出; 以及5）耦合在第二放大器级的输入和输出之间的内部补偿电容器。
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公开(公告)号：US5528185A
公开(公告)日：1996-06-18
申请号：US387169
申请日：1995-02-13
申请人： Laurence D. Lewicki , Ion E. Opris
发明人： Laurence D. Lewicki , Ion E. Opris
IPC分类号： H03K3/3565 , H03K3/037 , H03K3/356
CPC分类号： H03K3/3565
摘要： A comparator produces a digital output based upon a differential input signal and hysteresis. To inject positive feedback, a second differential pair is added. This feedback pair is nominally identical to the input pair. If the comparator has recently sensed a positive input of sufficient magnitude to drive the comparator output high, switches are turned on coupling a positive hysteresis voltage to the inputs of the feedback differential pair. By coupling a fixed current differential from the second differential pair to the input differential pair, the effective switching threshold of the comparator is changed. A non-overlapping clock generator is formed so that the switches will not turn on simultaneously so as to short the hysteresis reference voltage source. The hysteresis voltage source can be centered at any voltage that does not exceed the common mode range of the input pair. In a first alternative embodiment, the ratio of feedback is not unity, such that the hysteresis voltage is linearly related to the noise margin. In a second alternative embodiment, a more complicated switch matrix can be used to provide a variety of different hysteresis voltage levels. By including a more complicated switch matrix having several taps, the level of hysteresis can be made programmable. In a third alternative embodiment, the comparator structure according to the present invention is translated so that the differential pairs are formed with p-channel transistors. In a fourth alternative embodiment, the programmable hysteresis is applied to a sense amplifier.
摘要翻译： 比较器基于差分输入信号和滞后产生数字输出。 为了注入正反馈，添加了第二个差分对。 该反馈对名义上与输入对相同。 如果比较器最近感测到足够大的正输入以驱动比较器输出为高电平，则开关导通，将正滞后电压耦合到反馈差分对的输入端。 通过将来自第二差分对的固定电流差分耦合到输入差分对，比较器的有效开关阈值改变。 形成不重叠的时钟发生器，使得开关不会同时导通，以便使滞后参考电压源短路。 滞后电压源可以以不超过输入对的共模范围的任何电压为中心。 在第一替代实施例中，反馈比率不是一致的，使得滞后电压与噪声容限线性相关。 在第二替代实施例中，可以使用更复杂的开关矩阵来提供各种不同的滞后电压电平。 通过包括具有多个抽头的更复杂的开关矩阵，可以使滞后电平可编程。 在第三替代实施例中，根据本发明的比较器结构被转换，使得差分对由p沟道晶体管形成。 在第四替代实施例中，可编程滞后被应用于读出放大器。
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公开(公告)号：US06624704B1
公开(公告)日：2003-09-23
申请号：US10000194
申请日：2001-10-25
IPC分类号： H03F304
CPC分类号： H03F3/68 , H03F3/345 , H03F3/347 , H03F2200/72
摘要： An operational amplifier having a low impedance input and a high current gain output. The operational amplifier comprises: 1) a first N-channel transistor having a source coupled to the low impedance input of the operational amplifier; 2) a first constant current source coupled between the source of the first N-channel transistor and ground; 3) a first amplifier stage having an input coupled to the first N-channel transistor source and an inverting output coupled to a gate of the first N-channel transistor; 4) a second amplifier stage having an input coupled to a drain of the first N-channel transistor and an output coupled to the high current gain output of the operational amplifier; and 5) an internal compensation capacitor coupled between the input and the output of the second amplifier stage.
摘要翻译： 具有低阻抗输入和高电流增益输出的运算放大器。 运算放大器包括：1）具有耦合到运算放大器的低阻抗输入的源极的第一N沟道晶体管; 2）耦合在第一N沟道晶体管的源极与地之间的第一恒流源; 3）具有耦合到第一N沟道晶体管源的输入端和耦合到第一N沟道晶体管的栅极的反相输出的第一放大器级; 4）第二放大器级，其具有耦合到第一N沟道晶体管的漏极的输入端和耦合到运算放大器的高电流增益输出的输出; 以及5）耦合在第二放大器级的输入和输出之间的内部补偿电容器。
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公开(公告)号：US06559787B1
公开(公告)日：2003-05-06
申请号：US09911233
申请日：2001-07-23
IPC分类号： H03M138
CPC分类号： H03K3/013 , H03K3/356139 , H03K5/2481 , H03K5/249
摘要： There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.
摘要翻译： 公开了一种比较器，包括：1）能够接收输入信号的第一比较电路，其中所述第一比较电路被使能，并且当所接收的LATCH信号被使能时将所述信号进行比较，并且当所接收的LATCH信号被禁止时被禁用; 以及2）与所述第一比较电路并联耦合到所述输入信号的第二比较电路，其中所述第二比较电路的输入级基本上与所述第一比较电路的输入级相同。 当接收的LATCH信号被禁止时，第二比较电路被使能并比较输入信号，并且当所接收的LATCH信号被使能时被禁止。
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