公开(公告)号：US09070753B1

公开(公告)日：2015-06-30

申请号：US14327255

申请日：2014-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/7688 ,  H01L27/11573 ,  H01L29/66833

Abstract: Provided is a method for fabricating a memory device. A stack layer, including a storage layer, a first conductive layer and a first mask layer, is formed on the substrate in a first region and a second region. The stack layer is patterned to form a plurality of first patterned stack layers extending along a first direction and from the first region to the second region. Two sides of each first patterned stack layers have openings respectively. A filling layer is formed on the substrate, and filled in the openings. A second mask layer is formed on the second region, and does not cover the filling layer in the second region. Then, using the second mask layer and the filling layer as mask, the first patterned stack layers and part of the substrate are removed, and a plurality of trenches are formed in the substrate in the second region.

Abstract translation: 提供一种用于制造存储器件的方法。 在第一区域和第二区域中的衬底上形成包括存储层，第一导电层和第一掩模层的堆叠层。 图案化堆叠层以形成沿着第一方向从第一区域延伸到第二区域的多个第一图案化堆叠层。 每个第一图案化叠层的两侧分别具有开口。 填充层形成在基板上并填充在开口中。 第二掩模层形成在第二区域上，并且不覆盖第二区域中的填充层。 然后，使用第二掩模层和填充层作为掩模，去除第一图案化堆叠层和衬底的一部分，并且在第二区域中的衬底中形成多个沟槽。

公开(公告)号：US11690223B2

公开(公告)日：2023-06-27

申请号：US17160066

申请日：2021-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung Yi Lin ,  Chih-Hsiung Lee

IPC: H01L21/00 ,  H10B43/27 ,  H10B43/10 ,  H10B43/30

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/30

Abstract: Provided are a three-dimensional (3D) memory device and a manufacturing method thereof. The 3D memory device includes a gate stacked structure, a channel layer, a charge storage structure, an electrode layer and a capacitor dielectric layer. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The gate stacked structure has at least one channel hole and at least one capacitor trench. The channel layer is disposed on the sidewall of the at least one channel hole. The charge storage structure is disposed between the channel layer and the sidewall of the at least one channel hole. The electrode layer is disposed on the sidewall of the at least one capacitor trench. The capacitor dielectric layer is disposed between the electrode layer and the sidewall of the at least one capacitor trench.

公开(公告)号：US11348941B2

公开(公告)日：2022-05-31

申请号：US16856285

申请日：2020-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L27/11565 ,  H01L29/792 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105

Abstract: A memory device includes: first and second bit lines on a dielectric layer; first and second word lines between the first and second bit lines; a source line between the first and second word lines; a channel pillar penetrating through the first word line, the source line and the second word line, and connected to the first bit line, the source line, and the second bit line; a first charge storage structure surrounding a top surface and a bottom surface of the first word line and between a sidewall of the first word line and a lower portion of a sidewall of the channel pillar; and a second charge storage structure, surrounding a top surface and a bottom surface of the second word line and between a sidewall of the second word line and an upper portion of the sidewall of the channel pillar.

公开(公告)号：US20190198630A1

公开(公告)日：2019-06-27

申请号：US15849971

申请日：2017-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883

Abstract: Methods of managing gate coupling for semiconductor devices, e.g., non-volatile memory devices, are provided. The methods include: providing a conductive layer on a semiconductor substrate, the conductive layer including a lower conductive layer and an upper conductive layer, the lower conductive layer including a first material and the upper conductive layer including a second material having at least one property different from the first material, forming a protective pattern on the conductive layer, and etching through the conductive layer to obtain individual separated gates by controlling an etching process such that the first material has a higher etching rate than the second material during the etching process, each of the gates including an upper gate and a lower gate, the lower gate having a smaller width than the upper gate after the etching process.

公开(公告)号：US10304680B1

公开(公告)日：2019-05-28

申请号：US15851839

申请日：2017-12-22

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L21/033 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/788 ,  H01L21/762 ,  H01L29/06 ,  H01L21/027 ,  H01L21/28 ,  H01L29/66

Abstract: Methods of fabricating semiconductor devices having patterns with different feature sizes are provided. An example method includes: etching a first film layer below a patterned mask to form first and second features on a second film layer, forming respective first and second spacers adjacent to sidewalls of the first and second features on the second film layer, removing the first and second features to expose respective first and second portion of the second film layer, the second portion having a larger CD than the first portion, controlling an etching process such that the first portion is etched through and the second portion is protected from etching by a protective film formed during the etching process, and patterning a thin film masked by the first spacer, the second spacer, and the second portion to form smaller features and larger features in respective first and second regions of the thin film.

公开(公告)号：US09899396B1

公开(公告)日：2018-02-20

申请号：US15366682

申请日：2016-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L27/088 ,  H01L27/11524 ,  H01L27/11548 ,  H01L21/762 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L27/11531 ,  H01L27/11548

Abstract: A method for fabricating a semiconductor device includes: forming a first trench and a wider second trench in a substrate and a material layer formed thereon, forming a flowable isolation material covering the material layer and filling in the first and second trenches, removing a portion of the flowable isolation material in the second trench so that the thickness of the remaining flowable isolation material on the sidewall of the second trench is 200 Å to 1000 Å, and forming a non-flowable isolation material on the flowable isolation material.