公开(公告)号：US11182302B2

公开(公告)日：2021-11-23

申请号：US16820795

申请日：2020-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Lien Su ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F12/08 ,  G06F12/0882 ,  G06F12/0862 ,  G11C7/22 ,  G06F9/30 ,  G06F12/0893

Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

公开(公告)号：US09773571B2

公开(公告)日：2017-09-26

申请号：US14572166

申请日：2014-12-16

Applicant: Macronix International Co., Ltd.

Inventor： Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/00 ,  G11C29/00

CPC classification number: G11C29/78 ,  G06F2201/85 ,  G11C29/76

Abstract: An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.

公开(公告)号：US20160170853A1

公开(公告)日：2016-06-16

申请号：US14572166

申请日：2014-12-16

Applicant: Macronix International Co., Ltd.

Inventor： Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/20 ,  G11C29/00

CPC classification number: G11C29/78 ,  G06F2201/85 ,  G11C29/76

Abstract: An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.

Abstract translation: 描述了包括存储器，阵列高速缓存和高速缓存替换存储器的集成电路。 内存包括主阵列和冗余阵列。 集成电路还包括被配置为使用数组高速缓存将数据传入或传出主阵列的电路。 对于阵列高速缓存中的不良位置，电路被配置为在代替数据高速缓存中的有缺陷的位置的数据传输中使用高速缓存替换存储器，并且对应于高速缓存阵列中的缺陷位置的映射地址 到冗余阵列。

公开(公告)号：US09165680B2

公开(公告)日：2015-10-20

申请号：US14036997

申请日：2013-09-25

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

IPC: G11C29/04 ,  G11C29/00

CPC classification number: G11C29/70 ,  G11C29/04 ,  G11C29/72 ,  G11C29/808 ,  G11C29/82

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

Abstract translation: 集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。 主列和冗余列分为行块。 位线将主列连接到指示冗余列修复状态的状态存储器。 集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器执行更新。 或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

公开(公告)号：US08947961B2

公开(公告)日：2015-02-03

申请号：US13950942

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Lung Yi Kuo ,  Hsin Yi Ho ,  Chun Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen ,  Shih-Chou Juan

IPC: G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C16/10 ,  G11C29/04

CPC classification number: G11C16/10 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/4402

Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。

公开(公告)号：US20140254260A1

公开(公告)日：2014-09-11

申请号：US13946123

申请日：2013-07-19

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Ji-Yu Hung

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/28

Abstract: A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.

Abstract translation: 提供了一种用于感测存储器件中的数据的方法。 存储器件包括耦合到多个位线的存储器单元块。 该方法包括将多个位线预充电到第一级VPRE。 该方法包括实现电流流过多条位线上的选定存储单元到参考线或耦合到参考电压的参考线。 该方法包括防止由于位线上的电流而导致的电压变化导致位线电压超出第一电平和第二电平VKEEP之间的范围，其中第二电平低于第一电平， 高于参考电压。 该方法包括感测所选存储单元中的数据。

公开(公告)号：US08830754B2

公开(公告)日：2014-09-09

申请号：US13959780

申请日：2013-08-06

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C11/34

CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/32

Abstract: A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.

Abstract translation: 存储器访问方法应用于存储器控制器中，用于访问存储器阵列，包括由字符串选择信号全局控制的多个相应的选择开关。 存储器访问方法包括：在读取阶段之前启用字符串选择信号并禁用字符串选择信号。

公开(公告)号：US12131787B2

公开(公告)日：2024-10-29

申请号：US17891589

申请日：2022-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  E-Yuan Chang ,  Ji-Yu Hung

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H03K19/20

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  H03K19/20

Abstract: A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

公开(公告)号：US12020741B2

公开(公告)日：2024-06-25

申请号：US17838921

申请日：2022-06-13

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4096 ,  H03K19/20

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  H03K19/20

Abstract: Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.

公开(公告)号：US11815995B1

公开(公告)日：2023-11-14

申请号：US17730633

申请日：2022-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Che-Wei Liang ,  Shuo-Nan Hung ,  Hung-Wei Lu ,  Ming-Cheng Tu

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/0806 ,  G06F11/20 ,  G11C29/04 ,  G06F11/16

CPC classification number: G06F11/1064 ,  G06F11/1666 ,  G06F11/2017 ,  G06F12/0806 ,  G11C29/04 ,  G06F2212/62

Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.