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公开(公告)号：US09972383B2
公开(公告)日：2018-05-15
申请号：US15063756
申请日：2016-03-08
Applicant: Macronix International Co., Ltd.
Inventor： Chun Hsiung Hung , Han Sung Chen , Ming Chao Lin
CPC classification number: G11C11/5642 , G06F11/1048 , G06F11/108
Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.
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公开(公告)号：US10650887B2
公开(公告)日：2020-05-12
申请号：US15958360
申请日：2018-04-20
Applicant: Macronix International Co., Ltd.
Inventor： Chun Hsiung Hung , Han Sung Chen , Ming Chao Lin
Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.
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公开(公告)号：US20180240518A1
公开(公告)日：2018-08-23
申请号：US15958360
申请日：2018-04-20
Applicant: Macronix International Co., Ltd.
Inventor： Chun Hsiung Hung , Han Sung Chen , Ming Chao Lin
CPC classification number: G11C11/5642 , G06F11/1048 , G06F11/108
Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.
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公开(公告)号：US20140269074A1
公开(公告)日：2014-09-18
申请号：US13950942
申请日：2013-07-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Lung Yi KUO , Hsin Yi Ho , Chun Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen , Shih-Chou Juan
CPC classification number: G11C16/10 , G11C29/808 , G11C29/82 , G11C2029/4402
Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.
Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。
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公开(公告)号：US20140254257A1
公开(公告)日：2014-09-11
申请号：US14020684
申请日：2013-09-06
Applicant: Macronix International Co., Ltd.
Inventor： Hsin Yi Ho , Ming-Hsiu Lee , Chun Hsiung Hung , Hsiang-Lan Lung , Tien-Yen Wang
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0033 , G11C2013/0054
Abstract: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state.
Abstract translation: 一种用于管理存储器的方法包括将第一存储器单元的状态设置为表示第一数据的第一状态，并将第二存储单元的状态设置为表示第一数据的第二状态。 如果第二存储单元的状态已经改变为表示与第一数据不同的第二数据的第三状态，则该方法还包括将第二存储器单元的状态改变回第二状态。
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Patent Agency Ranking
公开(公告)号：US08787078B2
公开(公告)日：2014-07-22
申请号：US14105920
申请日：2013-12-13
Applicant: Macronix International Co., Ltd.
Inventor： Chun Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
CPC classification number: G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/3418
Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
Abstract translation: NAND存储器的各个方面包括控制电路，该控制电路通过测量在串联的第一端和第二端之间流动的电流来将读偏置装置施加到多个字线以读取存储在多个存储单元上的选定数据值 的记忆细胞。 读取偏置布置被施加到多个字线的字线仅施加小于第二阈值电压分布的第二最大值的字线电压。
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公开(公告)号：US09881654B2
公开(公告)日：2018-01-30
申请号：US14877723
申请日：2015-10-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wu-Chin Peng , Chun-Yi Lee , Ken-Hui Chen , Kuen-Long Chang , Chun Hsiung Hung
IPC: G11C5/14
CPC classification number: G11C5/145
Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.
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公开(公告)号：US09875811B2
公开(公告)日：2018-01-23
申请号：US14994472
申请日：2016-01-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chun Hsiung Hung , Shih Chou Juan , Nai-Ping Kuo , Yi Chun Liu
IPC: G11C29/50
CPC classification number: G11C29/50 , G11C7/02 , G11C11/5642 , G11C16/3427 , G11C29/24 , G11C29/50004 , G11C29/52
Abstract: A method for reading data from memory cells of a target word line in a semiconductor memory includes determining a disturbance status of the target word line. The disturbance status reflects a disturbance of a neighboring word line on the memory cells of the target word line. The method further includes determining a read voltage for the target word line according to the disturbance status of the target word line and applying the read voltage to the memory cells of the target word line.
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公开(公告)号：US20170263310A1
公开(公告)日：2017-09-14
申请号：US15063756
申请日：2016-03-08
Applicant: Macronix International Co., Ltd.
Inventor： Chun Hsiung Hung , Han Sung Chen , Ming Chao Lin
CPC classification number: G11C11/5642 , G06F11/1048 , G06F11/108
Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.
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公开(公告)号：US09558818B2
公开(公告)日：2017-01-31
申请号：US14020684
申请日：2013-09-06
Applicant: Macronix International Co., Ltd.
Inventor： Hsin Yi Ho , Ming-Hsiu Lee , Chun Hsiung Hung , Hsiang-Lan Lung , Tien-Yen Wang
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0033 , G11C2013/0054
Abstract: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state.
Abstract translation: 一种用于管理存储器的方法包括将第一存储器单元的状态设置为表示第一数据的第一状态，并将第二存储单元的状态设置为表示第一数据的第二状态。 如果第二存储单元的状态已经改变为表示与第一数据不同的第二数据的第三状态，则该方法还包括将第二存储器单元的状态改变回第二状态。
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