Abstract:
An electronic device including a touch sensor and a processing unit is provided. The touch sensor is disposed on or under a display, and generates touch data for a touch detected thereon or therenear when the electronic device is locked with the display in a sleep state. The processing unit determines whether the touch data matches a predetermined signature according to the touch data, and wakes the display from the sleep state and unlocks the electronic device when the touch data matches the predetermined gesture.
Abstract:
A method for controlling data transmission between a client device and a server is provided. The method includes the following steps: generating control information according to a data access rate of the client device and a data report rate of the server; and referring to the control information to manage at least one of a data access operation of the client device and a data reporting operation of the server.
Abstract:
A system for model protection includes a processor. The processor is arranged to execute a guest virtual machine (VM), a primary VM, and a hypervisor. The guest VM includes a model, and is arranged to send at least one command to a command hub. The primary VM is arranged to refer to the at least one command sent from the command hub to manage and configure a protection setting for a protected model derived from the model. The hypervisor is arranged to receive a safety setting command sent by the primary VM, and manage and configure the safety protection component according to the safety setting command, to set a read-only mode of the protected model.
Abstract:
A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.
Abstract:
A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.
Abstract:
A control system includes multiple device controllers and a device root. Each of the multiple device controllers corresponds to at least one processing unit, and is arranged to receive a hint from an application processor (AP), and generate a control signal for managing the at least one processing unit according to the hint. The device root is coupled to the multiple device controllers and includes a manager, wherein the manager is arranged to manage multiple processing units corresponding to the multiple device controllers according to multiple control signals corresponding to the multiple device controllers.
Abstract:
A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.
Abstract:
The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.
Abstract:
A microcontroller includes a processor, a memory, a working space management unit and a memory monitor. The memory has at least a working space, wherein the working space includes a plurality of blocks . The working space management unit is implemented by software, and is arranged for managing the working space of the first memory. The memory monitor is implemented by hardware circuit, and is arranged for monitoring the blocks, and recording monitoring results corresponding to the blocks of the first memory, wherein the recorded monitoring results comprise information about whether data of the blocks is modified or not.
Abstract:
A power-saving method and associated electronic device are provided. The electronic device is connected with a first external electronic device and a second external electronic device, and a first sensor and a second sensor are deployed on the first external electronic device and the second electronic device, respectively. The electronic device includes: a third sensor, and a processor, wherein the first, second, and third sensors have the same type. The processor gathers information from the first pedometer sensor, the second pedometer sensor, the first external electronic device, and the second external electronic device, and determines whether to turn off at least one of the first, second, and third pedometer sensors according to the information gathered.