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    SEMICONDUCTOR PACKAGE ASSEMBLY WITH THROUGH SILICON VIA INTERCONNECT
    11.
    发明申请
    SEMICONDUCTOR PACKAGE ASSEMBLY WITH THROUGH SILICON VIA INTERCONNECT 有权
    半导体封装通过互连的硅组件组装

    公开(公告)号：US20160181201A1

    公开(公告)日：2016-06-23

    申请号：US14963451

    申请日：2015-12-09

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN ,  Kuei-Ti CHAN ,  Ruey-Beei WU ,  Kai-Bin WU

    IPC: H01L23/538 ,  H01L25/065

    CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

    Abstract translation: 本发明提供一种具有TSV互连的半导体封装组件。 半导体封装组件包括安装在基座上的第一半导体管芯。 第一半导体管芯包括半导体衬底。 通过半导体衬底形成TSV互连的第一阵列和TSV互连的第二阵列，其中TSV互连的第一阵列和第二阵列被间隔区隔开。 第一接地TSV互连设置在间隔区域内。 第二半导体管芯安装在第一半导体管芯上，其上具有接地焊盘。 第一半导体管芯的第一接地TSV互连具有耦合到第二半导体管芯的接地焊盘的第一端子和耦合到布置在半导体衬底的前侧上的互连结构的第二端子。

    RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME
    13.
    发明申请
    RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
    无线电频率设备包及其制造方法

    公开(公告)号：US20150162242A1

    公开(公告)日：2015-06-11

    申请号：US14621703

    申请日：2015-02-13

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG

    IPC: H01L21/768 ,  H01L21/268 ,  H01L21/306 ,  H01L23/00

    CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.

    Abstract translation: 一种制造电子器件封装的方法，提供了一种电子器件芯片，其中电子器件芯片包括具有正面和背面的半导体衬底，其中半导体衬底具有第一厚度，电子部件设置在第一厚度的前侧 半导体衬底和布置在电子部件上的互连结构。 该方法还进行薄膜化处理以从背面去除半导体衬底的一部分。然后，该方法从薄化半导体的背面去除一部分减薄的半导体衬底和互连结构的介电层的一部分 衬底，直到互连结构的第一金属层图案被暴露，从而形成通孔。 最后，该方法在通孔中形成TSV结构，并将电子设备芯片安装在基座上。

    SEMICONDUCTOR CAPACITOR
    14.
    发明申请
    SEMICONDUCTOR CAPACITOR 审中-公开

    公开(公告)号：US20130249055A1

    公开(公告)日：2013-09-26

    申请号：US13893628

    申请日：2013-05-14

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong YANG

    IPC: H01L29/94

    CPC classification number: H01L29/94 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group.

    SEMICONDUCTOR STRUCTURE WITH THROUGH-SILICON VIA
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH THROUGH-SILICON VIA 有权
    通过硅的半导体结构

    公开(公告)号：US20160268183A1

    公开(公告)日：2016-09-15

    申请号：US15066256

    申请日：2016-03-10

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong YANG ,  Yu-Hua HUANG

    IPC: H01L23/48 ,  H01L27/02 ,  H01L27/092 ,  H01L23/532 ,  H01L29/06

    CPC classification number: H01L23/481 ,  H01L23/53295 ,  H01L27/0207 ,  H01L27/092

    Abstract: A semiconductor structure includes a semiconductor substrate and a conductive element formed in a portion of the semiconductor substrate. The semiconductor structure further includes a plurality of insulating elements formed in portions of the semiconductor substrate at a first region surrounding the conductive element and a semiconductor device formed over a portion of the semiconductor substrate at a second region adjacent to the first region. The first region is formed between the conductive element and the second region.

    Abstract translation: 半导体结构包括半导体衬底和形成在半导体衬底的一部分中的导电元件。 半导体结构还包括在围绕导电元件的第一区域处形成在半导体衬底的部分中的多个绝缘元件和在与第一区域相邻的第二区域处形成在半导体衬底的一部分上的半导体器件。 第一区域形成在导电元件和第二区域之间。

    PASSIVE DEVICE CELL AND FABRICATION PROCESS THEREOF
    19.
    发明申请
    PASSIVE DEVICE CELL AND FABRICATION PROCESS THEREOF 有权
    被动设备单元及其制造工艺

    公开(公告)号：US20160028359A1

    公开(公告)日：2016-01-28

    申请号：US14874888

    申请日：2015-10-05

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG

    IPC: H03H7/01

    CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

    Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.

    Abstract translation: 本发明的实施例涉及一种无源器件单元，其具有衬底层，以及形成在衬底层上方的中间层，以及形成在中间层上方的无源器件。 中间层包括多个LC谐振器和多个分段导电线，其中多个分段导线设置在多个LC谐振器之间。

    SEAL RING STRUCTURE WITH CAPACITOR
    20.
    发明申请
    SEAL RING STRUCTURE WITH CAPACITOR 有权
    密封圈结构与电容器

    公开(公告)号：US20140312470A1

    公开(公告)日：2014-10-23

    申请号：US14320725

    申请日：2014-07-01

    Applicant: MediaTek Inc.

    Inventor： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Yu-Hua HUANG ,  Ming-Tzong YANG

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

    Abstract translation: 半导体器件包括具有由密封环区域包围的芯片区域的第一导电类型的半导体衬底。 绝缘层位于半导体衬底上。 密封环结构埋设在对应于密封圈区域的绝缘层中。 并且，多个掺杂区域位于第一密封环结构下方。

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