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    Intelligent exposure of hardware latency statistics within an electronic device or system
    11.
    发明授权
    Intelligent exposure of hardware latency statistics within an electronic device or system 有权

    公开(公告)号：US12158795B2

    公开(公告)日：2024-12-03

    申请号：US18074751

    申请日：2022-12-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

    IPC: G06F1/04 ,  G06F11/07

    Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

    Network device safety protocol
    15.
    发明申请
    Network device safety protocol 有权

    公开(公告)号：US20230008730A1

    公开(公告)日：2023-01-12

    申请号：US17372555

    申请日：2021-07-12

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Sharon Ulman ,  Eyal Srebro ,  Shay Aisman

    IPC: H04L12/939 ,  H04L1/16 ,  H04L1/20 ,  H04L12/26 ,  H04L1/00

    Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.

    High-Frequency Event-Based Hardware Diagnostics
    16.
    发明申请
    High-Frequency Event-Based Hardware Diagnostics 有权

    公开(公告)号：US20220334939A1

    公开(公告)日：2022-10-20

    申请号：US17241079

    申请日：2021-04-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ran Koren ,  Shay Aisman ,  Itamar Rabenstein ,  Amir Ancel

    IPC: G06F11/273 ,  G06F11/22 ,  G06F13/20

    Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

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