公开(公告)号：US20230393770A1

公开(公告)日：2023-12-07

申请号：US17946518

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US11755884B2

公开(公告)日：2023-09-12

申请号：US16545813

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06N3/04 ,  G06N3/045 ,  G06N20/20 ,  G06N3/048

CPC classification number: G06N3/045 ,  G06N3/048 ,  G06N20/20

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.

公开(公告)号：US20230236747A1

公开(公告)日：2023-07-27

申请号：US18190669

申请日：2023-03-27

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Hongyu Wang ,  Justin M. Eno ,  Shivam Swami ,  Samuel E. Bradshaw

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0673 ,  G06F3/0607 ,  G06F12/1027

Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.

公开(公告)号：US11621029B2

公开(公告)日：2023-04-04

申请号：US17539052

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/22 ,  G11C11/16 ,  G11C11/408 ,  G11C13/00

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages configured to be refreshed according to a refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

公开(公告)号：US11481334B2

公开(公告)日：2022-10-25

申请号：US17319002

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US11416422B2

公开(公告)日：2022-08-16

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06K7/08 ,  G06K19/06 ,  G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F12/0802

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US20220237039A1

公开(公告)日：2022-07-28

申请号：US17723846

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  H04L41/0896 ,  G06F12/02 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US20210193209A1

公开(公告)日：2021-06-24

申请号：US16719907

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：US20210081336A1

公开(公告)日：2021-03-18

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US20210073622A1

公开(公告)日：2021-03-11

申请号：US16887665

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.