公开(公告)号：US20140087558A1

公开(公告)日：2014-03-27

申请号：US14097003

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

IPC: H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

公开(公告)号：US20190131315A1

公开(公告)日：2019-05-02

申请号：US16132984

申请日：2018-09-17

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatam Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11556 ,  H01L29/66 ,  H01L27/11524 ,  H01L29/788

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US20160284719A1

公开(公告)日：2016-09-29

申请号：US14666002

申请日：2015-03-23

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

Abstract translation: 一些实施例包括形成垂直堆叠的存储单元的方法。 通过交替的绝缘和导电水平的叠层形成开口。 腔体形成为延伸到沿开口侧壁的导电水平。 空腔中的至少一个形成为比空腔中的一个或多个更浅。 在腔内形成电荷阻挡电介质和电荷储存结构。 一些实施例包括具有交替的绝缘和导电水平的叠层的集成结构。 穴位扩展到导电水平。 至少一个空腔比空腔中的一个或多个其它孔更浅，至少约2纳米。 电荷阻挡电介质位于空腔内。 电荷存储结构位于空腔内。

公开(公告)号：US09431410B2

公开(公告)日：2016-08-30

申请号：US14069574

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

公开(公告)号：US09059115B2

公开(公告)日：2015-06-16

申请号：US14097003

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。