公开(公告)号：US20200027490A1

公开(公告)日：2020-01-23

申请号：US16038063

申请日：2018-07-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles L. Ingalls

IPC: G11C8/18 ,  G11C7/06 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08

Abstract: Apparatuses and methods for reducing rots address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

公开(公告)号：US10339985B2

公开(公告)日：2019-07-02

申请号：US16007022

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06 ,  G11C7/22 ,  H01L29/66 ,  H01L27/108 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US10163483B2

公开(公告)日：2018-12-25

申请号：US15844145

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US20180294015A1

公开(公告)日：2018-10-11

申请号：US16007022

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/067 ,  G11C2207/063 ,  H01L21/8221 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10897 ,  H01L29/7827

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US09941021B2

公开(公告)日：2018-04-10

申请号：US15184795

申请日：2016-06-16

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Charles L. Ingalls

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/70 ,  G11C2029/5006

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.

公开(公告)号：US09892776B2

公开(公告)日：2018-02-13

申请号：US15181188

申请日：2016-06-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C7/14 ,  G11C11/4099 ,  G11C5/06 ,  G11C11/22

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/4099 ,  G11C2211/5634

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US09858979B1

公开(公告)日：2018-01-02

申请号：US15286259

申请日：2016-10-05

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.

公开(公告)号：US20170365360A1

公开(公告)日：2017-12-21

申请号：US15184795

申请日：2016-06-16

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Charles L. Ingalls

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/70 ,  G11C2029/5006

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.

公开(公告)号：US09190126B2

公开(公告)日：2015-11-17

申请号：US14094466

申请日：2013-12-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC: G01R19/00 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

Abstract: Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

Abstract translation: 公开了用于预充电的感测放大器和方法，包括具有一对交叉耦合的互补晶体管反相器的读出放大器和一对晶体管，耦合到互补晶体管反相器中的相应一个的一对晶体管中的每一个， 。 感测放大器还包括耦合在该对晶体管之间的电容。 一种用于预充电的方法包括将读出放大器的输入节点耦合到预充电电压，将读出放大器的输入节点耦合在一起，并将电阻耦合到交叉耦合对的每个晶体管，以设置电压阈值（VT）失配补偿 每个晶体管的电压。 存储每个晶体管的VT失配补偿电压之间的电压差。

公开(公告)号：US20150049565A1

公开(公告)日：2015-02-19

申请号：US13970518

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Zhong-yi Xia ,  Scott J. Derner ,  Charles L. Ingalls ,  Howard C. Kirsch

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C16/28

Abstract: Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

Abstract translation: 描述了用于在存储器中操作读出放大器电路的装置，读出放大器电路和方法。 示例性装置包括读出放大器电路，其被配置为耦合到数字线并且被配置为在存储器访问操作期间将数字线驱动到指示由耦合到数字的存储器单元存储的电荷的逻辑值的电压 线。 在存储器访问操作的初始时间周期期间，读出放大器电路被配置为将数字线驱动到指示由存储器单元存储的电荷的逻辑值的第一电压。 在初始时间段之后，读出放大器电路被配置为将数字线驱动到不同于指示由存储器单元存储的电荷的逻辑值的第一电压的第二电压。