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    Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system
    11.
    发明授权
    Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system 有权

    公开(公告)号：US12014050B2

    公开(公告)日：2024-06-18

    申请号：US17889836

    申请日：2022-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Zhenming Zhou ,  Ching-Huang Lu ,  Murong Lang

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

    Adaptive enhanced corrective read based on write and read temperature
    12.
    发明授权
    Adaptive enhanced corrective read based on write and read temperature 有权

    公开(公告)号：US11947831B2

    公开(公告)日：2024-04-02

    申请号：US17830625

    申请日：2022-06-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu ,  Nagendra Prasad Ganesh Rao

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

    BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES
    15.
    发明公开
    BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES 审中-公开

    公开(公告)号：US20230197164A1

    公开(公告)日：2023-06-22

    申请号：US18076537

    申请日：2022-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

    IPC: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

    CPC classification number: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

    Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

    PROGRAM SCHEME FOR EDGE DATA WORDLINES IN A MEMORY DEVICE
    16.
    发明公开
    PROGRAM SCHEME FOR EDGE DATA WORDLINES IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230162796A1

    公开(公告)日：2023-05-25

    申请号：US17959171

    申请日：2022-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Hong-Yan Chen ,  Ching-Huang Lu

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

    CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

    Abstract: Control logic in a memory device causes a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of a memory array for a pulse duration period during a programming operation. The control logic further causes a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period and causes a second pass voltage to be applied to a last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the second pass voltage has a lower magnitude than the first pass voltage.

    MEMORY OPERATION BASED ON BLOCK-ASSOCIATED TEMPERATURE
    18.
    发明申请
    MEMORY OPERATION BASED ON BLOCK-ASSOCIATED TEMPERATURE 有权

    公开(公告)号：US20250013370A1

    公开(公告)日：2025-01-09

    申请号：US18890173

    申请日：2024-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Ching-Huang Lu ,  Devin Batutis

    IPC: G06F3/06 ,  G06F11/00 ,  G06F11/07

    Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

    3D NAND memory with built-in capacitor
    19.
    发明授权
    3D NAND memory with built-in capacitor 有权

    公开(公告)号：US12170117B2

    公开(公告)日：2024-12-17

    申请号：US17879356

    申请日：2022-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G11C16/30

    Abstract: An apparatus that includes a set of memory components of a memory sub-system is provided. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

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