公开(公告)号：US20230395135A1

公开(公告)日：2023-12-07

申请号：US17864046

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Innocenzo Tortorelli

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4076

Abstract: Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.

公开(公告)号：US11776590B2

公开(公告)日：2023-10-03

申请号：US17748866

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC classification number: G11C7/1009 ,  G11C7/06 ,  G11C7/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

公开(公告)号：US20230307042A1

公开(公告)日：2023-09-28

申请号：US17701463

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C13/00 ,  H01L27/11578 ,  G11C16/04

CPC classification number: G11C13/0026 ,  H01L27/11578 ,  G11C16/0483 ,  G11C13/0004 ,  G11C2213/71

Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

公开(公告)号：US20230282270A1

公开(公告)日：2023-09-07

申请号：US17686240

申请日：2022-03-03

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4082 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20230084481A1

公开(公告)日：2023-03-16

申请号：US18056516

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G06F11/07

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US20220399070A1

公开(公告)日：2022-12-15

申请号：US17343348

申请日：2021-06-09

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/02 ,  G11C11/4091

Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

公开(公告)号：US11495321B2

公开(公告)日：2022-11-08

申请号：US17387335

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/44 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02

Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.

公开(公告)号：US20220351758A1

公开(公告)日：2022-11-03

申请号：US17748866

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/10 ,  G11C29/42 ,  G11C16/10 ,  G11C16/26 ,  G11C7/06

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

公开(公告)号：US20220223187A1

公开(公告)日：2022-07-14

申请号：US17585307

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20220101917A1

公开(公告)日：2022-03-31

申请号：US17495423

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.