公开(公告)号：US10242742B2

公开(公告)日：2019-03-26

申请号：US15690497

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. A second set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

公开(公告)号：US10170196B2

公开(公告)日：2019-01-01

申请号：US15849267

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/26 ,  G11C8/08

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US20180114581A1

公开(公告)日：2018-04-26

申请号：US15849267

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US20140160851A1

公开(公告)日：2014-06-12

申请号：US13707067

申请日：2012-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/06

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US20200066350A1

公开(公告)日：2020-02-27

申请号：US16655826

申请日：2019-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Purval S. Sule ,  Han Liu ,  Andrea D'Alessandro ,  Pranav Kalavade ,  Han Zhao ,  Shantanu Rajwade

IPC: G11C16/12 ,  G11C16/34 ,  G11C11/4074 ,  G11C5/06 ,  G11C16/04

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

公开(公告)号：US20190147966A1

公开(公告)日：2019-05-16

申请号：US16228733

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US09773553B1

公开(公告)日：2017-09-26

申请号：US15241740

申请日：2016-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective first select gate and selectively connected to a common source through a corresponding respective second select gate. A first access line is coupled to a respective memory cell of a first position of each string of the plurality of strings. A second access line is coupled to a respective memory cell of a second position of each string of a first subset of the plurality of strings, and a third access line is coupled to a respective memory cell of the second position of each string of a second subset of the plurality of strings.

公开(公告)号：US09536618B2

公开(公告)日：2017-01-03

申请号：US14746416

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurielo Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/32 ,  G11C16/16 ,  G11C16/06 ,  G11C16/04 ,  G11C16/08 ,  G11C8/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US10854293B2

公开(公告)日：2020-12-01

申请号：US16868777

申请日：2020-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

公开(公告)号：US10777277B2

公开(公告)日：2020-09-15

申请号：US16655826

申请日：2019-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Purval S. Sule ,  Han Liu ,  Andrea D'Alessandro ,  Pranav Kalavade ,  Han Zhao ,  Shantanu Rajwade

IPC: G11C16/12 ,  G11C11/4074 ,  G11C16/04 ,  G11C16/34 ,  G11C5/06

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.